Doorbell Registers; Outbound Doorbell Register (Odr) - Freescale Semiconductor MPC8313E Family Reference Manual

DMA/Messaging Unit
12.3.5

Doorbell Registers

The following sections describe the outbound and inbound doorbell registers.
12.3.5.1

Outbound Doorbell Register (ODR)

ODR is accessible from the PCI bus and the CSB in both host and agent modes.
ODRn fields.
Offset: 0x060
31 29
R
—
W
Reset
15 14 13
R ODR
ODR ODR
15 14 13
W
Reset
Table 12-6 describes the ODR registers.
Bits Name
31–29 — Reserved
28–0 ODR n Outbound doorbell n.
Write 1 from the CSB to set.
Write 1 from the PCI bus to clear.
Writing 0 has no effect. (Writing a bit in this register from the CSB causes an interrupt (PCI_INTA) to be
generated.)
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
12-6
28 27 26 25
ODR ODR ODR ODR
28 27 26 25
12 11 10 9
ODR ODR ODR
ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0
12 11 10
Figure 12-6. Outbound Doorbell Register (ODR)
Table 12-6. ODR Field Descriptions
24 23 22 21
ODR ODR ODR ODR
24 23 22 21
All zeros
8 7 6 5
All zeros
Description
Figure 12-6 shows the
Access: Read/Write
20 19 18 17
ODR ODR ODR ODR
20 19 18 17
4 3 2 1
Freescale Semiconductor
16
ODR
16
0