Transmit Pause Control Frame Counter (Txpf); Transmit Deferral Packet Counter (Tdfr) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers

15.5.3.6.29 Transmit Pause Control Frame Counter (TXPF)

Figure 15-81 describes the definition for the TXPF register.
Offset eTSEC1:0x2_46F0; eTSEC2:0x2_56F0
0
R
W
Reset
Figure 15-81. Transmit Pause Control Frame Counter Register Definition
Table 15-85 describes the fields of the TXPF register.
Bits Name
0–15 — Reserved
16–31 TXPF Transmit PAUSE frame packet counter. Increments each time a valid PAUSE MAC control frame is
transmitted with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).

15.5.3.6.30 Transmit Deferral Packet Counter (TDFR)

Figure 15-82 describes the definition for the TDFR register.
Offset eTSEC1:0x2_46F4; eTSEC2:0x2_56F4
0
R
W
Reset
Figure 15-82. Transmit Deferral Packet Counter Register Definition
Table 15-86 describes the fields of the TDFR register.
Bits Name
0–19 — Reserved
20–31 TDFR Transmit deferral packet counter. Increments for each frame, which was deferred on its first transmission
attempt. This count does not include frames involved in collisions.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-94
—
All zeros
Table 15-85. TXPF Field Descriptions
—
All zeros
Table 15-86. TDFR Field Descriptions
15 16
Description
19 20
Description
Access: Read/Write
TXPF
Access: Read/Write
TDFR
Freescale Semiconductor
31
31