Inter-Packet Gap/Inter-Frame Gap Register (Ipgifg) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers
Bits Name
28 MPEN Magic packet enable for Ethernet modes. This bit is cleared by default. MPEN should be enabled only
after GRACEFUL RECEIVE STOP and GRACEFUL TRANSMIT STOP are completed successfully (in
other words, transmission and reception have stopped).
0 Normal receive behavior on receive, or Magic Packet mode has exited with reception of a valid
1 Commence Magic Packet detection by the MAC provided that frame reception is enabled in
29 PAD/CRC Pad and append CRC. This bit is cleared by default.This bit must be set when in half-duplex mode
(MACCFG2[Full Duplex] is cleared).
0 Frames presented to the MAC have a valid length and contain a CRC.
1 The MAC pads all transmitted short frames and appends a CRC to every frame regardless of
30 CRC EN CRC enable. If the configuration bit PAD/CRC ENABLE or the per-packet PAD/CRC ENABLE is set,
CRC ENABLE is ignored. This bit is cleared by default.
0 Frames presented to the MAC have a valid length and contain a valid CRC.
1 The MAC appends a CRC on all frames. Clear this bit if frames presented to the MAC have a valid
31 Full Full duplex configure. This bit is cleared by default.
Duplex 0 The MAC operates in half-duplex mode only.
1 The MAC operates in full-duplex mode.
15.5.3.5.3

Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG)

The IPGIFG register is written by the user.
Offset eTSEC1:0x2_4508; eTSEC2:0x2_5508
0 1
R
Non-Back-to-Back
—
Inter-Packet-Gap, Part 1
W
Reset 0 1 0 0 0
Table 15-43 describes the fields of the IPGIFG register.
Bits Name
0 —
1–7 Non-Back-to-Back
Inter-Packet-Gap, Part 1
8 —
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-70
Table 15-42. MACCFG2 Field Descriptions (continued)
Magic Packet.
MACCFG1. In this mode the MAC ignores all received frames until the specific Magic Packet frame
is received, at which point this bit is cleared by the eTSEC, and a maskable interrupt through
IEVENT[MAG] occurs.
padding requirement.
length and contain a valid CRC.
Figure 15-39
7 8 9
Non-Back-to-Back
—
Inter-Packet-Gap, Part 2
0 0 0 0 1 1 0 0
Figure 15-39. IPGIFG Register Definition
Table 15-43. IPGIFG Field Descriptions
Reserved
This is a programmable field representing the optional carrier sense window referenced in
IEEE 802.3/4.2.3.2.1 'carrier deference'. If carrier is detected during the timing of IPGR1,
the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC
continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair
access to medium. Its range of values is 0x00 to IPGR2. Its default is 0x40 (64d) which
follows the two-thirds/one-third guideline.
Reserved
Description
describes the definition for IPGIFG.
15 16
Minimum IFG
Enforcement
0 0 0 0 1 0 1 0
Description
Access: Read/Write
23 24 25
Back-to-Back
—
Inter-Packet-Gap
0 0 0 0 1 1 0 0
Freescale Semiconductor
31
0 0 0