Freescale Semiconductor MPC8313E Family Reference Manual page 399

Chapter 9
DDR Memory Controller
9.1 Introduction
The fully programmable DDR SDRAM controller supports most JEDEC standard ×8, ×16, or ×32 DDR2
and DDR memories available. In addition, unbuffered and registered DRAM modules are supported.
However, mixing different memory types or unbuffered and registered DRAM modules in the same system
is not supported. Dynamic power management and auto-precharge modes simplify memory system design.
A large set of special features support rapid system debug.
In this chapter, the word 'bank' refers to a physical bank specified by a chip
select; 'logical bank' refers to one of the four or eight sub-banks in each
SDRAM chip. A sub-bank is specified by the 2 or 3 bits on the bank address
(MBA) pins during a memory access.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
NOTE
9-1