Freescale Semiconductor MPC8313E Family Reference Manual page 423

Bits Name
0 MD_EN Mode enable
Setting this bit specifies that valid data in MD_VALUE is ready to be written to DRAM as one of the following
commands:
• MODE REGISTER SET
• EXTENDED MODE REGISTER SET
• EXTENDED MODE REGISTER SET 2
• EXTENDED MODE REGISTER SET 3
The specific command to be executed is selected by setting MD_SEL. In addition, the chip select must be
chosen by setting CS_SEL. MD_EN is set by software and cleared by hardware once the command has
been issued.
0 Indicates that no mode register set command needs to be issued.
1 Indicates that valid data contained in the register is ready to be issued as a mode register set command.
1 — Reserved
2–3 CS_SEL Select chip select
Specifies the chip select that is driven active due to any command forced by software in
DDR_SDRAM_MD_CNTL.
00 Chip select 0 is active
01 Chip select 1 is active
10 Reserved
11 Reserved
4 — Reserved
5–7 MD_SEL Mode register select
MD_SEL specifies one of the following:
• During a mode select command, selects the SDRAM mode register to be changed
• During a precharge command, selects the SDRAM logical bank to be precharged. A precharge all
command ignores this field.
• During a refresh command, this field is ignored.
Note that MD_SEL contains the value that is presented onto the memory bank address pins (MBA n ) of the
DDR controller.
000 MR
001 EMR
010 EMR2
011 EMR3
8 SET_REF Set refresh
Forces an immediate refresh to be issued to the chip select specified by
DDR_SDRAM_MD_CNTL[CS_SEL]. This bit is set by software and cleared by hardware once the
command has been issued.
0 Indicates that no refresh command needs to be issued.
1 Indicates that a refresh command is ready to be issued.
9 SET_PRE Set precharge
Forces a precharge or precharge all to be issued to the chip select specified by
DDR_SDRAM_MD_CNTL[CS_SEL]. This bit is set by software and cleared by hardware once the
command has been issued.
0 Indicates that no precharge all command needs to be issued.
1 Indicates that a precharge all command is ready to be issued.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 9-16. DDR_SDRAM_MD_CNTL Field Descriptions
Description
DDR Memory Controller
9-25