Pci Memory Map/Register Definitions - Freescale Semiconductor MPC8313E Family Reference Manual

Table 13-3. PCI Interface Signals—Detailed Signal Descriptions (continued)
Signal I/O
PCI_TRDY I/O PCI target ready.
O
I
13.3

PCI Memory Map/Register Definitions

The PCI controller has the following types of registers:
• The PCI configuration access registers. Used for generating PCI configuration accesses from the
CSB. These registers, listed in
the IMMR window.
• The PCI memory-mapped registers. Used to manage error functions, general control and status,
and address translation control for the inbound path. These registers are shown in
can be accessed by PCI masters via the PCI controller to the CSB through the PIMMR inbound
window. Note that
contained in the I/O sequencer (IOS) memory-mapped registers.
"DMA/Messaging Unit,"
• The PCI configuration space registers. Defined by the PCI specification. These registers are
accessed by PCI masters using configuration accesses and are described in
Configuration Space Registers."
Offset
PCI Configuration Access Registers—Block Base Address 0x0_8300
0x00 PCI_CONFIG_ADDRESS
0x04 PCI_CONFIG_DATA
0x08 PCI_INT_ACK
0x80 PCIPMR0—PCI power management register 0
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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Outputs for the bi-directional target ready.
State Asserted—The PCI controller, acting as a PCI target, can complete the current data
Meaning phase of a PCI transaction. During a read, this PCI controller asserts PCI_TRDY to
indicate that valid data is present on PCI_AD[31:0]. During a write, this PCI
controller asserts PCI_TRDY to indicate that it is prepared to accept data.
Negated—The PCI initiator needs to wait before this PCI controller, acting as a PCI target,
can complete the current data phase. During a read, this PCI controller negates
PCI_TRDY to insert a wait cycle when it cannot provide valid data to the initiator.
During a write, this PCI controller negates PCI_TRDY to insert a wait cycle when it
cannot accept data from the initiator.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Inputs for the bi-directional target ready.
State Asserted—Another PCI target is able to complete the current data phase of a transaction.
Meaning Negated—A wait cycle from another target.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Table 13-4, are memory-mapped on the CSB and accessed through
Table 13-5 does not list outbound address translation registers; these are
for more information.
Table 13-4. PCI Configuration Access Registers
Register
Description
SeeChapter 12,
Access Reset
W All zeros
R/W All zeros
R N/A
R 0x7E4B_0001
PCI Bus Interface
Table 13-5. They
Section 13.3.3, "PCI
Section/Page
13.3.1.1/13-13
13.3.1.2/13-14
13.3.1.3/13-15
13.3.3.27/13-41
13-11