Freescale Semiconductor MPC8313E Family Reference Manual page 430

DDR Memory Controller
Figure 9-20 shows an example DDR SDRAM configuration with four logical banks.
MCS, MRAS, MCAS, MWE
CKE, MCK, MCK
Figure 9-20. Typical Dual Data Rate SDRAM Internal Organization
Figure 9-21 shows some typical signal connections.
BANK ADDR
Figure 9-22 shows an example DDR SDRAM configuration with two physical banks each comprised of
four 8M × 8 DDR modules for a total of 128 Mbytes of system memory. Certain address and control lines
may require buffering. Analysis of the device's AC timing specifications, desired memory operating
frequency, capacitive loads, and board routing loads can assist the system designer in deciding signal
buffering requirements. The DDR memory controller drives 15 address pins, but in this example the DDR
SDRAM devices use only 12 bits.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
9-32
SDRAM
ADDR
COMMAND:
DQM Control
BA1,BA0
13
ADDR A[12:0]
'SUB' 2
BA[1:0]
MRAS
MCAS
MWE
MCS
DM Write Enable
CKE
MCK
MCK
Figure 9-21. Typical DDR SDRAM Interface Signals
Data Bus
Data-Out Registers
MUX, MASK,
Read Data Latch
Logical Logical
Bank 0 Bank 1
64M × 1 Byte
512 Mbit
8
DQ[7:0]
DQS
Command
Bus
CK
Data-In Registers
Logical Logical
Bank 2 Bank 3
DATA
DATA
STROBE
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