Pci Error Control Register (Pci_Ecr) - Freescale Semiconductor MPC8313E Family Reference Manual

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shows the bit settings of PCI_GCR. The bits that are not reserved have read and write

PCI Error Control Register (PCI_ECR)

PCI_ECR contains fields for determining whether an interrupt or machine check is generated for the error

conditions reported in the PCI error status register (PCI_ESR). Note that if the corresponding bit in the

PCI error enable register (PCI_EER) is clear, the bit in the PCI error control register (PCI_ECR) has no

1 = A machine check is generated.

0 = An interrupt is generated.

Figure 13-13

shows the PCI_ECR fields.

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

Figure 13-12. PCI General Control Register (PCI_GCR)

Table 13-15. PCI_GCR Field Descriptions

Block bus requests. This bit could be used to prepare for entering a low-power mode by preventing

transactions on the PCI bus.

0 External bus requests are treated normally.

1 Block external bus requests. When this bit is set, all bus requests from external devices to the

PCI controller's internal arbiter are blocked, and the bus is continuously granted to the PCI

PCI pins low. This bit could be used to put the bus signals in a safe electrical state when the devices

on the bus are powered down. This bit should never be set during normal operation of the PCI bus.

0 PCI pins function normally

1 PCI pins in the low state. Setting this bit forces all the output and bidirectional pins of the PCI bus

to be driven low.

Soft PCI reset. This bit provides software control of the PCI_RESET_OUT output signal. It is only

valid in host mode.

0 PCI_RESET_OUT is driven low.

1 PCI_RESET_OUT is driven high.

Figure 13-13. PCI Error Control Register (PCI_ECR)

APAR PCISERR MPERR TPERR NORSP TABT

PCI Bus Interface

Access: Read/Write

BBR PPL SPRST

Access: Read/Write

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