Local Bus Controller Setting When Loading Rcw; Using The Boot Sequencer Reset Configuration - Freescale Semiconductor MPC8313E Family Reference Manual

The device will use PCI_SYNC_IN clock to generate the internal LCLK, which will run at half the
frequency of PCI_SYNC_IN.
CFG_RESET_SOURCE
0000
0001
0101
4.3.3.2 Loading from I
The device is capable of loading the reset configuration word from the I
2
I C interfaces, but only I
configuration word from the I
2
I C unit boot sequencer in a special mode. In this mode, the I
of the device is still in reset state (HRESET asserted) to load the reset configuration words from an I
serial EEPROM.
Note that this does not prevent using the I
mode after reset state has completed. The only restriction is that the first two EEPROM data structures
contain dedicated reset information.
4.3.3.2.1

Using the Boot Sequencer Reset Configuration

For a detailed description about the I
Sequencer Mode."
When reset configuration words are loaded from an I
serial EEPROM of extended addressing type must be used.
2
If the I C interface is used for loading the reset configuration words, the I
EEPROM and reads the first two data structures (after reading the preamble). Upon being read, the reset
configuration words are latched inside the device and the I
is negated. There should be no other I
After HRESET is negated, the functional boot sequencer, in extended I
activated if the BOOTSEQ field of the reset configuration word high is set to 0b10.
4.3.3.2.2 EEPROM Calling Address
The device uses 0b101_0000 for the EEPROM calling address. The EEPROM to be addressed must
contain the reset configuration information and be programmed to respond to this address. No additional
EEPROMs are accessed by the boot sequencer in reset configuration mode.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 4-22. Local Bus Controller Setting when Loading RCW
Meaning
NOR Flash
NAND Flash, 8 bit,
small page
NAND Flash, 8 bit,
large page
2
C EEPROM
2
C #1 can be used for this purpose). If the device is configured to load the reset
2
C interface, according to the reset configuration input signals, it uses the
2
C boot sequencer to initiate the device in the normal functional
2
C interface and the boot sequencer refer to
2
C traffic when the boot sequencer is active.
BR0[PS] BR0[MSEL]
10 000
01 001
01 001
2
C boot sequencer is activated while the rest
NOTE
2
C EEPROM, an I
2
C module enters its reset state until HRESET
Reset, Clocking, and Initialization
OR0[SCY] OR0[PGS]
1111 NA
0010 0
0010 1
2
C interfaces (the device has two
Section 17.4.5, "Boot
2
C
2
C module addresses the
2
C addressing mode, may be
2
C
4-23