Freescale Semiconductor MPC8313E Family Reference Manual page 737

Table 15-1. eTSEC n Network Interface Signal Properties (continued)
Signal Name
TSEC n _TX_CLK MII—transmit clock, input
RMII—reference transmit and receive clock, input
RGMII, RTBI—unused
TSEC n _TXD[3:0] MII—Transmit data bits 3:0, output
RGMII (TX_CLK rising)—Transmit data bits 3:0, output
RGMII (TX_CLK falling)—Transmit data bits 7:4, output
RTBI (TX_CLK rising)—TCG bits 3:0, output
RTBI (TX_CLK falling)—TCG bits 8:5, output
RMII—TXD[1:0] transmit data bits, output
RMII—TXD[3:2] unused
TSEC n _TX_ER MII—transmit error, output
RGMII, RTBI, RMII—unused, output driven zero
TSEC n _TX_EN MII, RMII—Transmit data valid, output
RGMII (TX_CLK rising)—Transmit data enabled, output
RGMII (TX_CLK falling)—Transmit error, output
RTBI (TX_CLK rising)—TCG bit 4, output
RTBI (TX_CLK falling)—TCG bit 9, output
TSEC_1588_CLK 1588—Clock input
External high precision timer reference clock input (chip external input pin).
TSEC_1588_GCLK 1588—Clock output
Phase aligned timer clock divider output (chip external output pin).
TSEC_1588_TRIG1 1588—Trigger in 1
External timer trigger input 1. This is an asynchronous general purpose input (chip external
input pin).
TSEC_1588_TRIG2 1588—Trigger in 2
External timer trigger input 2. This is an asynchronous general purpose input (chip external
input pin).
TSEC_1588_PP1 1588—Pulse out 1
Timer pulse per period 1. It is phase aligned with 1588 timer clock (chip external output pin).
TSEC_1588_PP2 1588—Pulse out 2
Timer pulse per period 2. It is phase aligned with 1588 timer clock (chip external output pin).
TSEC_1588_PP3 1588—Pulse out 3
Timer pulse per period 3. It is phase aligned with 1588 timer clock (chip external output pin).
TSEC_1588_ALARM1 1588—Timer alarm 1
Timer current time is equal to or greater than alarm time comparator register. User
reprograms the TSEC_1588_ALARM n _H/L register to deactivate this output (chip external
output pin).
TSEC_1588_ALARM2 1588—Timer alarm 2
Timer current time is equal to or greater than alarm time comparator register. User
reprograms the TSEC_1588_ALARM n _H/L register to deactivate this output (chip external
output pin).
SD_REF_CLK, SerDes PLL reference clock (and complement)
SD_REF_CLK
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Enhanced Three-Speed Ethernet Controllers
Function
Reset
State
—
0000
0
0
—
0
—
—
0
0
0
0
0
—
15-7