Basic Architecture; Address And Address Space Checking - Freescale Semiconductor MPC8313E Family Reference Manual

Address
Comparator
Bank Select
MSEL
Field
Figure 10-29. Basic Operation of Memory Controllers in the eLBC
Each memory bank (chip select) can be assigned to any of these three types of machines through the
machine select bits of the base register for that bank (BRn[MSEL]), as illustrated in
match occurs, the corresponding machine (GPCM, FCM, or UPM) then takes ownership of the external
signals that control the access and maintains control until the transaction ends.
Different machines (FCM/GPCM/UPM) share the address, data, and
control signals. While the eLBC is servicing a transaction, subsequent
transactions are queued until the current transaction has completed.
10.4.1

Basic Architecture

The following subsections describe the basic architecture of the eLBC.
10.4.1.1

Address and Address Space Checking

The defined base addresses are written to the BRn registers, while the corresponding address masks are
written to the ORn registers. Each time a local bus access is requested, the internal transaction address is
compared with each bank. Addresses are decoded by comparing the 17 MSBs of the address, masked by
ORn[AM], with the base address for each bank (BRn[BA]). If a match is found on a memory controller
bank, the attributes defined in the BRn and ORn for that bank are used to control the memory access. If a
match is found in more than one bank, the lowest-numbered bank handles the memory access (that is, bank
0 has priority over bank 1).
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Internal Memory Access Request Select
32-bit System
Address
UPM A/B/C
32-bit Physical
RAM Address (A)
FCM buffer
RAM
FCM
Signals Timing Generator
External Signals
NOTE
Enhanced Local Bus Controller
GPCM
Figure 10-29. If a bank
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