Dual Enhanced Three-Speed Ethernet Controllers - Freescale Semiconductor MPC8313E Family Reference Manual

• Many different SDRAM configurations supported
— Support for as many as two physical banks (chip selects), each bank independently addressable
— Support for 64-Mbit to 1-Gbit devices with x8/x16/x32 data ports. Some 2-Gbit devices are
supported depending on the internal device configuration.
— Support for unbuffered and registered
• Support for data mask signals and read-modify-write operations for sub-double word writes
• Four-entry input request queue
• Open page management (dedicated entry for each sub-bank)
• Memory controller clock frequency of two times the SDRAM clock with support for sleep power
management mode
1.2.4

Dual Enhanced Three-Speed Ethernet Controllers

The MPC8313E has two on-chip enhanced three-speed Ethernet controllers. The eTSECs incorporate a
media access control (MAC) sublayer that supports 10- and 100-Mbps and 1-Gbps Ethernet/IEEE Std.
802.3 networks with MII, RMII, RGMII, RTBI, and SGMII physical interfaces. The eTSECs include
2-Kbyte receive and 10-Kbyte transmit FIFOs and DMA functions. They also support IEEE Std. 1588.
The buffer descriptors are based on the MPC8260 and MPC860T 10/100 Ethernet programming models.
Each eTSEC can emulate a PowerQUICC III TSEC, allowing existing driver software to be re-used with
minimal change.
The MPC8313E eTSECs support programmable CRC generation and checking, RMON statistics, and
jumbo frames of up to 9.6 Kbytes. Frame headers and buffer descriptors can be forced into the L2 cache
to speed classification or other frame processing.
Each eTSEC provides hardware support for accelerating TCP/IP packet transmission and reception. By
default, TCP/IP acceleration is not enabled, and the eTSEC processes frames as pure Ethernet frames.
TCP/IP acceleration can be performed at a number of levels. The eTSEC can parse frames at layer 2 of the
stack only (Ethernet headers and switching headers), layers 2 to 3 (including IP v4 or IP v6), or layers 2
to 4 (including TCP and UDP).
On receive, the eTSEC provides protocol header recognition, header verification (IP v4 header checksum
verification), and TCP/UDP payload checksum verification including verification of associated
pseudo-header checksums. On transmit, the eTSEC provides IP v4 and TCP/UDP header checksum
generation. The eTSEC does not checksum transmitted packets with IP header options or IP fragments.
To provide for quality of service, transmission from up to eight queues is supported with priority-based
queue selection. Arbitration is a modified weighted round-robin queue selection with fair bandwidth
allocation.
On receive, packets may be distributed to any of the 64 virtual receive queues overlaid onto the 8 physical
receive queues. A table-oriented queue filing strategy is provided based on 16 header fields or flags. Frame
rejection is supported for filtering applications.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Overview
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