Interrupt Coalescing; Interrupt Coalescing By Frame Count Threshold - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers
• Clear any set halt or frame interrupt bits in TSTAT and RSTAT registers, or DMACTRL[GTS] and
DMACTRL[GRS] by writing 1s to these bits.
• Continue normal execution.
Interrupt
GTSC Graceful transmit stop complete: transmitter is put into a pause state
after completion of the frame currently being transmitted.
TXC Transmit control: Instead of the next transmit frame, a control frame
was sent.
TXB Transmit buffer: A transmit buffer descriptor, that is not the last one in
the frame, was updated in one of the enabled TxBD rings.
TXF Transmit frame: A frame from an enabled TxBD ring was transmitted
and the last transmit buffer descriptor (TxBD) of that frame was
updated.
Interrupt
GRSC Graceful receive stop complete: Receiver is put into a pause state after
completion of the frame currently being received.
RXC Receive control: A control frame was received. As soon as the
transmitter finishes sending the current frame, a pause operation is
performed.
RXB Receive buffer: A receive buffer descriptor, that is not the last one of
the frame, was updated in one of the enabled RxBD rings.
RXF Receive frame: A frame was received to an enabled RxBD ring and the
last receive buffer descriptor (RxBD) of that frame was updated.

15.6.2.10.1 Interrupt Coalescing

Interrupt coalescing offers the user the ability to contour the behavior of the eTSEC with regard to frame
interrupts. Separate but identical mechanisms exist for both transmitted frames and received frames. In
either case, frame interrupts require that software set the I-bit in RxBDs or TxBDs, and disable buffer
interrupts (IEVENT[RXB] or IEVENT[TXB]). Particular rings can remain free of interrupts by ensuring
that the I-bit is consistently cleared in all BDs. While interrupt coalescing is enabled, a transmit or receive
frame interrupt is raised either when a counter threshold-defined number of frames is received/transmitted
or the timer threshold-defined period of time has elapsed, whichever occurs first. Disabling and then
re-enbling interrupt coalescing forces reset of the coalescing timers and counters to reflect changes made
to the threshold registers.

15.6.2.10.2 Interrupt Coalescing By Frame Count Threshold

To avoid interrupt bandwidth congestion due to frequent, consecutive interrupts, the user may enable and
configure interrupt coalescing to deliberately group frame interrupts, reducing the total number of
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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Table 15-145. Non-Error Transmit Interrupts
Description
Table 15-146. Non-Error Receive Interrupts
Description
Action Taken by the eTSEC
None
None
Programmable 'write with response' TxBD
to memory before setting IEVENT[TXB].
Programmable 'write with response' to
memory on the last TxBD before setting
IEVENT[TXF].
Action Taken by the eTSEC
None
None
Programmable 'write with response' RxBD
to memory before setting IEVENT[RXB].
Programmable 'write with response' to
memory on the last RxBD before setting
IEVENT[RXF].
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