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4.1.2
Clock Signals
In
Table
4-2, some clock signals are specific to blocks within the device. Although some of their
functionality is described in
See
Figure 4-7
for the internal distribution of clocks in the device.
Signal
I/O
SYS_CLK_IN
I
SYS_CR_CLK_IN
I
SYS_CR_CLK_OUT
O
USB_CLK_IN
I
USB_CR_CLK_IN
I
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Section 4.4, "Clocking,"
Table 4-2. External Clock Signals
System clock. In PCI host mode, SYS_CLK_IN is the primary input clock. SYS_CLK_IN directly
feeds the PCI output clock dividers and is driven out on the PCI_SYNC_OUT signal for de-skewing
external PCI clocks routing. If the device is used as PCI agent, PCI_CLK can be provided from a
PCI source. In this case, SYS_CLK_IN may no longer be needed and should be tied low. If
SYS_CLK_IN is the clock source, SYS_CR_CLK_IN should be tied low and SYS_CR_CLK_OUT
should be left unconnected.
Timing Assertion/Negation—See the hardware specifications for timing information.
Requirements Should be tied low if unused, for example in PCI agent mode or when the clock is
provided through SYS_CR_CLK_IN.
Reset State Always input.
Crystal input. SYS_CR_CLK_IN/SYS_CR_CLK_OUT allows the system clock to be provided
using an external crystal oscillator. If a crystal source is used, SYS_CLK_IN should be tied low.
Timing Assertion/Negation—See the hardware specifications for timing information.
Requirements Should be tied low if unused, for example in PCI agent mode or when the clock is
provided through SYS_CLK_IN.
Reset State Always input.
Crystal output. SYS_CR_CLK_IN/SYS_CR_CLK_OUT allows the system clock to be provided
through an external crystal oscillator. If a crystal source is used, SYS_CLK_IN should be tied low.
Timing Assertion/Negation—See the hardware specifications for timing information
Requirements Should be left unconnected if unused, for example in PCI agent mode or when the
clock is provided through SYS_CLK_IN.
Reset State Always output.
USB PHY clock. USB_CLK_IN feeds into the USB PHY PLL.
Timing Assertion/Negation—See the hardware specifications for timing information.
Requirements Should be tied low if unused, for example when the clock is provided through
USB_CR_CLK_IN or when derived from the system clock.
Reset State Always input.
USB crystal input. USB_CR_CLK_IN/USB_CR_CLK_OUT allows the USB clock to be provided
using an external crystal oscillator. If a crystal source is used, USB_CLK_IN should be tied low.
Timing Assertion/Negation—See the hardware specifications for timing information.
Requirements Should be tied low if unused, for example when the clock is provided through
USB_CR_CLK_IN or when derived from the system clock.
Reset State Always input.
they are defined in detail in their respective chapters.
Description
Reset, Clocking, and Initialization
4-3
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