Serial Interface; Start Bit; Data Transfer; Parity Bit - Freescale Semiconductor MPC8313E Family Reference Manual

18.4.1

Serial Interface

The UART bus is a serial, full-duplex, point-to-point bus as shown in
devices are attached to the same signals and there is no need for address or arbitration bus cycles.
rxcnt
1 2
SOUT1 D6 D5 D4 D3 D2 D1 D0 PTY
Variable Data Bits
START
Figure 18-16. UART Bus Interface Transaction Protocol Example
A standard UART bus transfer is composed of either three or four parts:
•

START bit

• Data transfer (least significant bit is first data bit on the bus)
• Parity bit (optional)
• STOP bits
An internal logic sample signal, rxcnt, uses the frequency of the baud-rate generator to drive the bits on
SOUT.
The following sections describe the four components of the serial interface, the baud-rate generator, local
loopback mode, different errors, and FIFO mode.
18.4.1.1 START Bit
A write to UTHR generates a START bit on the SOUT signal.
defined as a logic 0. The START bit denotes the beginning of a new data transfer which is limited to the
bit length programmed in ULCR.When the bus is idle, SOUT is high.
18.4.1.2

Data Transfer

Each data transfer contains 5, 6, 7, or 8 bits of data. The ULCR data bit length for the transmitter and
receiver UART devices must agree before a transfer begins; otherwise, a parity or framing error may occur.
A transfer begins when UTHR is written. At that time, a START bit is generated followed by 5 to 8 of the
data bits previously written to the UTHR. The data bits are driven from the least- to the most-significant
bits. After the parity and STOP bits, a new data transfer can begin if new data is written to UTHR.
18.4.1.3

Parity Bit

The user has the option of using even, odd, no parity, or stick parity (see
Registers (ULCR1 and ULCR2)."
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
3 4 5 6 7 8
STOP Bits
Optional
Even/Odd Parity
Two 7-Bit Data Transmissions with Parity and 2-Bit STOP Transactions
Both the receiver and transmitter parity definitions must agree before
9 10 1 2 3
D6 D5 D4 D3 D2 D1 D0 PTY
Figure 18-16
Figure 18-16. Therefore, only two
4 5 6 7 8 9
Data Bits
STOP Bits
shows that the START bit is
Section 18.3.1.8, "Line Control
DUART
10
18-19