Receive Descriptor Base Address Registers (Rbase0–Rbase); Receive Stamp Register (Tmr_Rxts_H/L) - Freescale Semiconductor MPC8313E Family Reference Manual

Offset eTSEC1:0x2_4384+8× n ; eTSEC2:0x2_5384+8× n
0
R
W
Reset
Table 15-38 describes the fields of the RBPTRn register.
Bits Name
0–28 RBPTR n Current RxBD pointer for RxBD ring n . Points to the current BD being processed or to the next BD the
receiver uses when it is idling. After reset or when the end of the RxBD ring is reached,
eTSEC initializes RBPTR n to the value in the corresponding RBASE n . The RBPTR register is internally
written by the eTSEC's DMA controller during reception. The pointer increments by 8 (bytes) each time a
descriptor is closed successfully by the eTSEC. Note that the 3 least-significant bits of this register are
read only and zero.
29–31 — Reserved
15.5.3.3.12 Receive Descriptor Base Address Registers (RBASE0–RBASE7)
The RBASEn registers are written by the user with the base address of each RxBD ring n. Each such value
must be divisible by eight, since the 3 least-significant bits always write as 000.
RBASEn registers.
Offset eTSEC1:0x2_4404+8× n ; eTSEC2:0x2_5404+8× n
0
R
W
Reset
Table 15-39 describes the fields of the RBASEn registers.
Bits Name
0–28 RBASE n Receive base for ring n . RBASE defines the starting location in the memory map for the eTSEC RxBDs.
This field must be 8-byte aligned. Together with setting the W (wrap) bit in the last BD, the user can select
how many BDs to allocate for the receive packets. The user must initialize RBASE before enabling the
eTSEC receive function on the associated ring.
29–31 — Reserved

15.5.3.3.13 Receive Stamp Register (TMR_RXTS_H/L)

Receive time stamp register (RXTS_H/L). This register holds the value present in TMR_CNT_H/L when
the eTSEC detects a new incoming Ethernet frame. This register is only updated when the precision time
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
RBPTR n
Figure 15-34. RBPTR0–RBPTR7 Register Definition
Table 15-38. RBPTR n Field Descriptions
RBASE n
Figure 15-35. RBASE Register Definition
Table 15-39. RBASE0–RBASE7 Field Descriptions
Enhanced Three-Speed Ethernet Controllers
All zeros
Description
All zeros
Description
Access: Read/Write
28 29
—
Figure 15-35 describes the
Access: Read/Write
28 29
—
15-63
31
31