System Internal Interrupt Group D Priority Register (Siprr_D) - Freescale Semiconductor MPC8313E Family Reference Manual

Integrated Programmable Interrupt Controller (IPIC)
Offset 0x10
0 2 3
R
SYSA0P SYSA1P
W
Reset 0 0 0 0 0
Figure 8-6. System Internal Interrupt Group A Priority Register (SIPRR_A)
Table 8-11 defines the bit fields of SIPRR_A.
Bits Name
0–2 SYSA0P
3–11, 16–27 SYSA1P–SYSA7P Same as SYSA0P, but for SYSA1P–SYSA7P.
12–15, 28–31 —
8.5.5

System Internal Interrupt Group D Priority Register (SIPRR_D)

SIPRR_D, shown in Figure
Offset 0x1C
0 2 3
R
SYSD0P SYSD1P SYSD2P SYSD3P
W
Reset 0 0 0 0 0
Figure 8-7. System Internal Interrupt Group D Priority Register (SIPRR_D)
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
8-14
5 6 8 9 11 12
SYSA2P SYSA3P
1 0 1 0 0 1 1 0
Table 8-11. SIPRR_A Field Descriptions
SYSA0 priority order. Defines which interrupt source asserts its request in the SYSA0
priority position. The user should not program the same code to multiple priority positions
(0–7). These bits can be changed dynamically. The definition of SYSA0P is as follows:
000 TSEC1 Tx asserts its request in the SYSA0 position.
001 TSEC1 Rx asserts its request in the SYSA0 position.
010 TSEC1 Err asserts its request in the SYSA0 position.
011 TSEC2 Tx asserts its request in the SYSA0 position.
100 TSEC2 Rx asserts its request in the SYSA0 position.
101 TSEC2 Err asserts its request in the SYSA0 position.
110 USB DR asserts its request in the SYSA0 position.
111 Reserved
Write ignored, read = 0
8-7, defines the priority among the interrupt sources listed in
5 6 8 9 11 12
1 0 1 0 0 1 1 0
15 16 18 19
— SYSA4P SYSA5P
0 0 0 1 0 0 1 0
Description
15 16 18 19
SYSD4P SYSD5P SYSD6P SYSD7P
—
0 0 0 1 0 0 1 0
Access: Read/write
21 22 24 25 27 28
SYSA6P SYSA7P
1 1 1 0 1 1 1 0
Table
Access: Read/write
21 22 24 25 27 28
1 1 1 0 1 1 1 0
Freescale Semiconductor
31
—
0 0 0
8-12.
31
—
0 0 0