Freescale Semiconductor MPC8313E Family Reference Manual page 941

Table 15-177. SGMII Mode Register Initialization Steps (continued)
Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register. (Optional)
(Uses the PHY address (0x10) and Register address (5) placed in MIIMADD register),
read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10. (Half and Full Duplex)
MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_000x_1110_0000]
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Setup MIIMADD[0000_0000_0000_0000_0001_0000_0000_0101]
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY] = 0,
Clear IEVENT register,
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize IMASK (Optional)
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACnADDR1/2 (Optional)
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize GADDR n (Optional)
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
Initialize RCTRL (Optional)
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize DMACTRL (Optional)
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize (Empty) Transmit Descriptor ring and fill buffers with Data
Initialize TBASE0–TBASE7,
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
Initialize RBASE0–RBASE7,
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Enable Transmit Queues
Initialize TQUEUE
Enable Receive Queues
Initialize RQUEUE
Enable Rx and Tx,
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]
Enhanced Three-Speed Ethernet Controllers
15-211