Modem Control Registers (Umcr1 And Umcr); Line Status Registers (Ulsr1 And Ulsr) - Freescale Semiconductor MPC8313E Family Reference Manual

DUART
18.3.1.9 MODEM Control Registers (UMCR1 and UMCR2)
The UMCRs, shown in
UART bus.
Offset: 0x0_4504, 0x0_4604
0
R
W
Reset
Table 18-16 describes the UMCR fields.
.
Bits Name
0–2 — Reserved, should be cleared
3 LOOP Local loopback mode
0 Normal operation.
1 Functionally, the data written to UTHR can be read from URBR of the same UART, and UMCR[RTS] is tied
to UMSR[CTS].
4–5 — Reserved
6 RTS Ready to send
0 Negates corresponding UART_RTS output.
1 Assert corresponding UART_RTS output. Informs external MODEM or peripheral that the UART is ready
for sending/receiving data.
7 — Reserved
18.3.1.10 Line Status Registers (ULSR1 and ULSR2)
The ULSRs, shown in
the status bits from the proper character received through the UART bus, software should read the ULSR
and then the URBR.
Offset: 0x0_4505, 0x0_4605
0
R RFE
W
Reset 0
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
18-14
Figure 18-11, control the interface with the external peripheral device on the
1 2
—
Figure 18-11. Modem Control Register (UMCR1 and UMCR2)
Table 18-16. UMCR Field Descriptions
Figure 18-12, monitor the status of the data transfer on the UART buses. To isolate
1 2
TEMT THRE
1 1
Figure 18-12. Line Status Register (ULSR1 and ULSR2)
3 4
LOOP —
All zeros
Description
3 4
BI FE
0 0
Access: Read/write
5 6
RTS
Access: Read-only
5 6
PE OE
0 0
Freescale Semiconductor
7
—
7
DR
0