System Internal Interrupt Mask Register (Simsr_H And Simsr_L) - Freescale Semiconductor MPC8313E Family Reference Manual

Table 8-12 defines the bit fields of SIPRR_D.
Bits Name
0–2 SYSD0P SYSD0 priority order. Defines which interrupt source asserts its request in the SYSD0 priority position. The
user should not program the same code to more than one priority position (0–7). These bits can be changed
dynamically. SYSD0P is defined as follows:
000 UART1 asserts its request in the SYSD0 position.
001 UART2 asserts its request in the SYSD0 position.
010 SEC asserts its request in the SYSD0 position.
011 eTSEC1 1588 timer asserts its request in the SYSD0 position.
100 eTSEC2 1588 timer asserts its request in the SYSD0 position.
101 I2C1 asserts its request in the SYSD0 position.
110 I2C2 asserts its request in the SYSD0 position.
111 SPI asserts its request in the SYSD0 position.
3–11, SYSD1P– Same as SYSD0P, but for SYSD1P–SYSD7P.
16–27 SYSD7P
12–15, — Write ignored, read = 0
28–31
8.5.6

System Internal Interrupt Mask Register (SIMSR_H and SIMSR_L)

Each implemented bit in SIMSR_H and SIMSR_L, shown in
internal interrupt source. The user masks an interrupt by clearing the corresponding SIMSR bit. When an
interrupt request occurs, the corresponding SIPNR bit is set, regardless of the SIMSR bit. However, if the
corresponding SIMSR bit is cleared, no interrupt request is passed to the core.
When an SIMSR bit is cleared by the user at the same time corresponding interrupt source requests an
interrupt service, the request stops. If the user sets the SIMSR bit later, the core processes any pending
corresponding interrupt requests according to its priority.
Offset 0x20
0
R
W
Reset
Figure 8-8. System Internal Interrupt Mask Register (SIMSR_H)
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 8-12. SIPRR_D Field Descriptions
n (Implemented bits are listed in
INT
All zeros
Integrated Programmable Interrupt Controller (IPIC)
Description
Figure 8-8 and Figure
Table 8-7.)
8-9, corresponds to an
Access: Read/write
31
8-15