Sicrh Bit Settings - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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System Configuration

Offset 0x00118

defines the bit fields of SICRH. Each Pin Function column lists the name of the multi-function

pin used in this option. Some groups have only two options (shown as Pin Function 0 and Pin Function 1)

and therefore, only one control bit. In this case they can have the value of 0b0 or 0b1 only. Other groups

may have three options (shown as Pin Function 0, Pin Function 1, and Pin Function 2) and therefore, two

control bits. In this case they can have the value of 0b00, 0b01, or 0b10. A value of 0b11 selects GPIO

mode of the appropriate pin. Use the 0bN or 0bNN notations according to a group having one or two

control bits, respectively.

Note that bits 30 and 31 (TSOBI1 and TSOBI2), which control TSEC output buffer impedance, are

described in

SICRH[Bits] Value:

Pin Function 0

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Depends on reset configuration

Depends on reset configuration

Depends on reset configuration

Depends on reset configuration

Figure 5-15. System I/O Configuration Register High (SICRH)

Table 5-28. SICRH Bit Settings

Pin Function 1

Pin Function 2

Access: Read/Write

Pin Function 3

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