Freescale Semiconductor MPC8313E Family Reference Manual page 160

Signal Descriptions
Table 3-2. MPC8313E Signal Reference by Signal Name (continued)
Name
MCKE DDR clock enable
MCP_OUT Machine check
interrupt output
MCS[0:1] DDR chip select
(2/DIMM)
MDM[0:3] DDR data mask
MDQ[0:31] DDR data
MDQS[0:3] DDR data strobe
MDVAL Memory debug data
valid
MDVAL Memory debug data
valid
MODT[0:1] DRAM on-die
termination
MRAS DDR row address
strobe
MSRCID[0:4] Memory debug
source ID 0–4
MSRCID0 Memory debug
source ID 0
MSRCID1 Memory debug
source ID 1
MSRCID2 Memory debug
source ID 2
MSRCID3 Memory debug
source ID 3
MSRCID4 Memory debug
source ID 4
MWE DDR write enable
PCI_AD[31:0] PCI address/data
PCI_C/BE[3:0] PCI command/byte
enable
PCI_CLK0 PCI clock 0
PCI_CLK1 PCI clock 1
PCI_CLK2 PCI clock 2
PCI_CLOCK/ PCI clock/PCI clock
PCI_SYNC_IN sync input
PCI_DEVSEL PCI device select
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
3-22
Functional
Description
Block
DDR
IPIC
DDR
DDR
DDR
DDR
Debug
Debug
DDR
DDR
Debug
Debug
Debug
Debug
Debug
Debug
DDR
PCI
PCI
PCI
PCI
PCI
Clocks
PCI
No. of Table/
I/O
Signals Page
1 O 9-4/9-7
1 O 8-2/8-5
2 O 9-3/9-5
4 O 9-3/9-5
32 I/O 9-3/9-5
4 I/O 9-3/9-5
1 I/O 9-1/9-3
1 I/O 9-1/9-3
2 O 9-3/9-5
1 O 9-3/9-5
5 I/O 9-1/9-3
1 I/O 9-1/9-3
1 I/O 9-1/9-3
1 I/O 9-1/9-3
1 I/O 9-1/9-3
1 I/O 10-2/10-5
1 O 9-3/9-5
32 I/O 13-3/13-5
4 I/O 13-3/13-5
1 O 4-2/4-3
1 O 4-2/4-3
1 O 4-2/4-3
1 I 4-2/4-3
1 I/O 13-3/13-5
Alternate Table/
Function(s) Page
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LA[5]/GPIO[5] 10-2/10-5,
21-1/21-2
UART_SIN2 18-2/18-3
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—
LA[0:4]/GPIO[0:4] 10-2/10-5,
21-1/21-2
UART_SOUT1 18-2/18-3
UART_SIN1 18-2/18-3
UART_CTS1/GPIO[8] 18-2/18-3,
21-1/21-2
UART_RTS1/GPIO[9] 18-2/18-3,
21-1/21-2
UART_SOUT2 18-2/18-3
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