Arbiter Event Response Register (Aerr) - Freescale Semiconductor MPC8313E Family Reference Manual

Table 6-9 describes AEADR fields.
Bits Name
0–31 ADDR Address of the event reported in AEATR register. See
(AEATR),"
6.2.9

Arbiter Event Response Register (AERR)

Arbiter event response register (AERR) determines whether different error conditions cause interrupt or
reset request. Setting a bit defines the corresponding error condition to cause reset request; clearing a bit
defines the corresponding error condition to cause interrupt.
Offset 0x20
0
R
W
Reset
Table 6-10 describes AERR field.
Bits Name
0–25 — Write reserved, read = 0
26 ETEA Transfer error. Detection of transfer error by one of the slaves event response.
0 Detection of transfer error by one of the slaves causes interrupt.
1 Detection of transfer error by one of the slaves causes reset request.
27 RES Reserved transfer type. Transaction with reserved transfer type interrupt definition.
0 Transaction with reserved transfer type causes interrupt.
1 Transaction with reserved transfer type causes reset request.
28 ECW External control word transfer type. Transaction with external control word transfer type interrupt
definition.
0 Transaction with external control word transfer type causes interrupt.
1 Transaction with external control word transfer type causes reset request.
29 AO Address only transfer type. Transaction with address only transfer type interrupt definition.
0 Transaction with address only transfer type causes interrupt.
1 Transaction with address only transfer type causes reset request.
30 DTO Data time out. Data tenure time out interrupt definition.
0 Data tenure time out causes interrupt.
1 Data tenure time out causes reset request.
31 ATO Address time out. Address tenure time out interrupt definition.
0 Address tenure time out causes interrupt.
1 Address tenure time out causes reset request.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 6-9. AEADR Field Descriptions
for more information.
—
Figure 6-9. Arbiter Event Response Register (AERR)
Table 6-10. AERR Field Descriptions
Description
Section 6.2.7, "Arbiter Event Attributes Register
Figure 6-9 shows the fields of AERR.
25
All zeros
Description
Arbiter and Bus Monitor
Access: Read/write
26 27 28 29 30
ETEA RES ECW AO DTO ATO
31
6-11