Freescale Semiconductor MPC8313E Family Reference Manual page 494

Enhanced Local Bus Controller
Offset FECC0: 0x100
FECC1: 0x104
FECC2: 0x108
FECC3: 0x10C
0 1
R V
—
W
Reset
Bits Name
0 V Valid bit. This bit denotes that the ECC stored in this register is valid. It is set for full page write/read
transfers if ECC generation/checking is enabled in BR n [DECC].
1–7 — Reserved
8–31 ECC 24 bit ECC; For n
page where k = 0,1,2,...). It stores calculated ECC value during writes/reads.
10.4 Functional Description
The eLBC allows the implementation of memory systems with very specific timing requirements.
• The GPCM provides interfacing for simpler, lower-performance memories and memory-mapped
devices. It has inherently lower performance because it does not support bursting. For this reason,
GPCM-controlled banks are used primarily for boot-loading from NVRAM or NOR Flash, and
access to low-performance memory-mapped peripherals.
• The FCM interfaces the eLBC to NAND Flash EEPROMs with 8-bit data bus. The FCM has an
automatic boot-loading feature that allows the CPU to boot from high density EEPROM, loading
the boot block into 4 Kbytes of RAM for execution of the first level boot code. Following boot,
FCM provides a flexible instruction sequencer that allows a user-defined command, address, and
data transfer sequence of up to 8 steps to be executed against a memory-mapped buffer RAM.
Programmable set-up time, hold time, and wait states permit the FCM to maximize the
performance of NAND Flash block transfers, which can proceed in parallel with software
processing of the multiple RAM buffers. A single-pass ECC engine in the FCM permits
zero-overhead error checking, reporting, and correction in both boot blocks and page data transfers
if enabled.
• The UPM supports refresh timers, address multiplexing of the external bus, and generation of
programmable control signals for row address and column address strobes, to allow for a minimal
glue logic interface to DRAMs, burstable SRAMs, and almost any other kind of peripheral with
asynchronous timing or single data rate clocking. The UPM can be used to generate flexible,
user-defined timing patterns for control signals that govern a memory device. These patterns define
how the external control signals behave during a read, write, burst-read, or burst-write access.
Refresh timers are also available to periodically initiate user-defined refresh patterns.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
10-40
7 8
Figure 10-28. Flash ECC Block n Register (FECC0–FECC3)
Table 10-31. FECC n Field Descriptions
th
512 bytes of a page in case of large page or for (4 k + n)
ECC
All zeros
Description
Access: Read Only
th
512 byte page for small
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