System Mixed Interrupt Group B Priority Register (Smprr_B) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor
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Table 8-17
defines the bit fields of SMPRR_A.
Bits
Name
0–2
MIXA0P MIXA0 priority order. Defines which interrupt source asserts its request in the MIXA0 priority position. The
user must not program the same code to more than one priority position (0–7). These bits can be changed
dynamically. The definition of MIXA0P is as follows:
000 RTC SEC asserts its request to the MIXA0 position.
001 PIT asserts its request to the MIXA0 position.
010 PCI asserts its request to the MIXA0 position.
011 Reserved.
100 IRQ0 asserts its request to the MIXA0 position. This field for MIXA0 position is valid (must not be
ignored) if IRQ0 signal configured as an external maskable interrupt (SEMSR[SIRQ0] = 0).
101 IRQ1 asserts its request to the MIXA0 position.
110 IRQ2 asserts its request to the MIXA0 position.
111 IRQ3 asserts its request to the MIXA0 position.
3–11,
MIXA1P–
Same as MIXA0P, but for MIXA1P–MIXA7P.
16–27
MIXA7P
12–15,
Write ignored, read = 0
28–31
8.5.10

System Mixed Interrupt Group B Priority Register (SMPRR_B)

SMPRR_B, shown in
Figure
Offset 0x34
0
2
3
R
MIXB0P
MIXB1P
W
Reset 0
0
0
0
0
Figure 8-13. System Mixed Interrupt Group B Priority Register (SMPRR_B)
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 8-17. SMPRR_A Field Descriptions
8-13, defines the priority among the sources listed in
5
6
8
9
11 12
MIXB2P
MIXB3P
1
0
1
0
0
1
1
0
Integrated Programmable Interrupt Controller (IPIC)
Description
15 16
18 19
MIXB4P
MIXB5P
0
0
0
1
0
0
1
0
Table
8-18.
Access: Read/write
21 22
24 25
27 28
MIXB6P
MIXB7P
1
1
1
0
1
1
1
0
31
0
0
0
8-19

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