Freescale Semiconductor MPC8313E Family Reference Manual page 967

Powerquicc ii pro integrated processor
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ULPI VIEWPORT is shown in
Offset 0x170
31
30
R
ULPIWU ULPIRUN ULPIRW
W
Reset
15
R
W
Reset
Table 16-21
describes the ULPI register access fields.
Bits
Name
31
ULPIWU
30
ULPIRUN
29
ULPIRW
28
27
ULPISS
26–24
ULPIPORT
23–16
ULPIADDR
15–8
ULPIDATRD
7–0
ULPIDTWR
There are two operations that can be performed with the ULPI viewport, wakeup and read /write
operations. The wakeup operation is used to put the ULPI interface into normal operation mode and
re-enable the clock if necessary. A wakeup operation is required before accessing the registers when the
ULPI interface is operating in low power mode, serial mode, or carkit mode. The ULPI state can be
determined by reading the sync state bit (ULPISS). If this bit is set, then the ULPI interface is running in
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Figure
16-18.
29
28
27
26
ULPISS
ULPIPORT
ULPIDATRD
Figure 16-18. ULPI Register Access (ULPI VIEWPORT)
Table 16-21. ULPI VIEWPORT Field Descriptions
ULPI Wake Up. Writing 1 to this bit begins the wakeup operation. This bit automatically
transitions to 0 after the wakeup is complete. Once this bit is set, it can not be cleared by
software.
Note: The driver must never execute a wakeup and a read/write operation at the same time.
ULPI Run. Writing 1 to this bit begins a read/write operation. This bit automatically transitions
to 0 after the read/write is complete. Once this bit is set, it can not be cleared by software.
Note: The driver must never execute a wakeup and a read/write operation at the same time.
This bit selects between running a read or write operation to the ULPI.
0 Read
1 Write
Reserved, should be cleared.
This bit represents the state of the ULPI interface. Before reading this bit, the ULPIPORT field
should be set accordingly if used with the multi-port host. Otherwise, this field should always
remain 0.
0 Any other state (that is, carkit, serial, low power).
1 Normal Sync State.
For wakeup or read/write operations this value selects the port number to which the ULPI PHY
is attached. Valid values are 0 and 1.
When a read or write operation is commanded, the address of the operation is written to this
field.
After a read operation completes, the result is placed in this field.
When a write operation is commanded, the data to be sent is written to this field.
24
23
All zeros
8
7
All zeros
Description
Universal Serial Bus Interface
Access: Mixed
ULPIADDR
ULPIDTWR
16
0
16-25

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