Freescale Semiconductor MPC8313E Family Reference Manual page 288

System Configuration
• Generating or responding to appropriate control signals relative to low power modes: VDD
switching control (EXT_PWR_CTRL) output signal and input signal indicating external power is
stable (PMC_PWR_OK)
The relationship between the e300 core and the defined PMC power states is illustrated in
The relationships shown below between e300 core doze, nap, and sleep
modes and PCI D-states are only suggested. There is no forced hardware
relationship between these states. For example, if a PCI host sets
PCIPMR1[Power_State] = 01, it is still up to the software running on the
e300 to put itself into doze mode.
Table 5-73. Software-Controller Power-Down States—Basic Description
System Core Suggested
Mode Mode PCI D- state
Full On Full
(PMCCR[SL On PCIPMR1[P
PEN]=0) owerState]=
Doze
PCIPMR1[P
owerState]=
Nap
PCIPMR1[P
owerState]=
Sleep
PCIPMR1[P
owerState]=
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
5-78
Description
D0 All units operating normally
00
D1 Core stops dispatching new instructions
(core is halted), and most of the core
functional units are disabled. System
01 operates normally.
D2 Core is stopped with its clocks off except to
time base. System operates normally.
10
D2 Core is stopped with its clocks off. Core
clocks powered down to all blocks (including
core time base) except to the
10 interrupt unit. System operates normally.
NOTE
Core Responds
Snoop Interrupt
Yes
Yes
No
No
Table 5-73.
DDR Quiesce
to
SDRAM Signal
strl state
Yes Active Negated
Yes Active Negated
Yes Active Negated
Yes Active Negated
Freescale Semiconductor
State