Etsec Transmit Control And Status Registers; Transmit Control Register (Tctrl) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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Enhanced Three-Speed Ethernet Controllers

Offset eTSEC1:0xB_0030; eTSEC2:0xB_1030

describes the fields of the TBIPA register.

TBIPA This field is used to program the PHY address of the ten-bit interface's MII management bus. To access the

TBI register the user must write the TBIPA value to the MIIMADD [PHY Address] register located in the MAC

eTSEC Transmit Control and Status Registers

This section describes the control and status registers that are used specifically for transmitting Ethernet

frames. All of the registers are 32 bits wide.

This register is writable by the user to configure the transmit block.

Offset eTSEC1:0x2_4100; eTSEC2:0x2_5100

describes the fields of the TCTRL register.

IP header checksum generation enable. When set, the eTSEC offloads IPv4 header checksum

generation. See

0 IP header checksum generation is disabled even if enabled in a transmit frame control block.

1 IP header checksum generation is performed for IPv4 headers as determined by the settings in the

current transmit frame control block.

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Figure 15-10. TBIPA Register Definition

Table 15-15. TBIPA Field Descriptions

IPCSEN TUCSEN VLINS THDF

Figure 15-11. TCTRL Register Definition

Table 15-16. TCTRL Field Descriptions

Section 15.6.3.2, "Transmit Path Off-Load and Tx PTP Packet Parsing," on

Section 15.5.3.5.8, "MII Management Address Register

Figure 15-11

Access: Read/Write

describes the TCTRL

TFC_PAUSE TXSCHED —

Freescale Semiconductor

Access: Mixed

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