Deu Data Size Register (Deudsr) - Freescale Semiconductor MPC8313E Family Reference Manual

0
Field
Reset
R/W
Addr
Table 14-12 shows the DEUKSR fields.
Bits Name
0–51 — Reserved
52–63 Key Size 8 bytes = 0x08 (only legal value if mode is single DES)
16 bytes = 0x10 (for 2 key 3DES, K1 = K3)
24 bytes = 0x18 (for 3 key 3DES)
14.4.1.3

DEU Data Size Register (DEUDSR)

The DEU data size register (DEUDSR), shown in
message block, which must be 64. All data to be processed by the DEU must be a multiple of the DES
algorithm block size of 64 bits; the DEU does not automatically pad messages out to 64-bit blocks. If a
data size that is not a multiple of 64 bits is written, a data size error will be generated. Only bits 58–63 are
checked to determine if there is a data size error. Since all upper bits are ignored, the entire message length
(in bits) can be written to this register.
DEUDSR is cleared when the DEU is reset or re-initialized.
0
Field
Reset
R/W
Addr
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
—
DEU 0x3_2008
Figure 14-8. DEU Key Size Register (DEUKSR)
Table 14-12. DEUKSR Field Descriptions
Figure
—
DEU 0x3_2010
Figure 14-9. DEU Data Size Register (DEUDSR)
51 52
0
R/W
Description
14-9, stores the number of bits in the final
51 52
0
R/W
Security Engine (SEC) 2.2
63
Key Size (bytes)
63
Data Size (bits)
14-21