Gpcm Read Signal Timing - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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Enhanced Local Bus Controller

chip-select is available that provides a boot ROM chip-select (LCS0) prior to the system being fully

eLBC in GPCM

Figure 10-33

shows LCS as defined by the setup time required between the address lines and CE. The user

can configure ORn[ACS] to specify LCS to meet this requirement. Generally, the attributes for the

memory cycle are taken from ORn. These attributes include the CSNT, ACS, XACS, SCY, TRLX, EHTR,

and SETA fields.

Figure 10-33. GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0, CLKDIV = 4,8)

GPCM Read Signal Timing

The basic GPCM read timing parameters that may be set by the ORn attributes are shown in

The read access cycle commences upon latching of the memory address (LALE negated), and concludes

when LBCTL returns high to turn the local bus around for a subsequent address phase. Read data is

captured by eLBC on the falling edge of TA. LOE and LCSn negate high simultaneously, in some cases

before the end of the read access to provide additional hold time for the external memory.

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Figure 10-32. Enhanced Local Bus to GPCM Device Interface

Memory/Peripheral

Latched Address

Freescale Semiconductor

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