Freescale Semiconductor MPC8313E Family Reference Manual page 655

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Security Engine (SEC) 2.2

This chapter describes the functionality of the integrated security engine (SEC 2.2) in the MPC8313E. It

addresses the following topics:

Section 14.1, "SEC 2.2 Architecture Overview"

Section 14.2, "Configuration of Internal Memory Space"

Section 14.3, "Descriptor Overview"

Section 14.4, "Execution Units"

Section 14.5, "Channel"

Section 14.6, "Controller"

The MPC8313 does not support a security engine.

The SEC 2.2 is designed to off-load computationally intensive security functions, such as authentication,

and bulk encryption from the processor core of the MPC8313E. It is optimized to process all the algorithms

associated with IPSec, SSL/TLS, iSCSI, SRTP, and 802.11i. The SEC 2.2 is derived from integrated

security cores found in other members of the PowerQUICC family, including SEC 1.0, the version

implemented in the MPC8272 and SEC 2.0, implemented on the MPC8555.

The security engine's execution units (EUs) and primary features include the following:

DEU—Data encryption standard execution unit

— Two key (K1, K2, K1) or three key (K1, K2, K3)

— ECB and CBC modes for both DES and 3DES

AESU—Advanced encryption standard execution unit

— Implements the Rinjdael symmetric key cipher

— ECB, CBC, CCM, and counter modes

— 128-, 192-, 256-bit key lengths

MDEU—Message digest execution unit

— SHA with 160-, 224-, or 256-bit message digest

— MD5 with 128-bit message digest

— HMAC with either algorithm

One channel, supporting a queue of commands (descriptor pointers)

— Dynamic assignment of execution units through an integrated controller

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

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