Mac Configuration 2 Register (Maccfg) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers
Bits Name
24–25 — Reserved
26 Rx_Flow Receive flow. This bit is cleared by default.
Must be 0 if MACCFG2[Full Duplex] = 0.
0 The receive MAC control ignores PAUSE flow control frames.
1 The receive MAC control detects and acts on PAUSE flow control frames.
Note: Should not be set when operating in Half-Duplex mode
27 Tx_Flow Transmit flow. This bit is cleared by default.
Must be 0 if MACCFG2[Full Duplex] = 0.
0 The transmit MAC control may not send PAUSE flow control frames if requested by the system.
1 The transmit MAC control may send PAUSE flow control frames if requested by the system.
Note: Should not be set when operating in Half-Duplex mode
28 Sync'd Rx EN Receive enable synchronized to the receive stream. (Read-only)
0 Frame reception is not enabled.
1 Frame reception is enabled.
29 Rx_EN Receive enable. This bit is cleared by default. If set, prior to clearing this bit, set DMACTRL[GRS] then
confirm subsequent occurrence of the graceful receive stop interrupt (IEVENT[GRSC] is set).
0 The MAC may not receive frames from the PHY.
1 The MAC may receive frames from the PHY.
30 Sync'd Tx EN Transmit enable synchronized to the transmit stream. (Read-only)
0 Frame transmission is not enabled.
1 Frame transmission is enabled.
31 Tx_EN Transmit enable. This bit is cleared by default. If set, prior to clearing this bit, set DMACTRL[GTS] then
confirm subsequent occurrence of the graceful transmit stop interrupt (IEVENT[GTSC] is set).
0 The MAC may not transmit frames from the system.
1 The MAC may transmit frames from the system.
15.5.3.5.2 MAC Configuration 2 Register (MACCFG2)
The MACCFG2 register is written by the user.
register.
Offset eTSEC1:0x2_4504; eTSEC2:0x2_5504
0
R
W
Reset
16 19 20 21 22
R Preamble
—
Length
W
Reset 0 1 1 1 0 0
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-68
Table 15-41. MACCFG1 Field Descriptions (continued)
23 24
I/F
PreAmRxEN PreAmTxEN
Mode
0 0 0
Figure 15-38. MACCFG2 Register Definition
Description
Figure 15-38 describes the definition for the MACCFG2
—
All zeros
25 26 27
Huge Length
Frame check
0 0 0
Access: Read/Write
28 29 30
MPEN PAD/CRC CRC EN
0 0 0
Freescale Semiconductor
15
31
Full
Duplex
0