Output Clock Control Register (Occr) - Freescale Semiconductor MPC8313E Family Reference Manual

Reset, Clocking, and Initialization
4.5.2.2

Output Clock Control Register (OCCR)

The OCCR shown in Figure
clock modes by writing to this memory mapped register as described below.
Addre 0x0_0A04
ss
0 1
R
PCICOE PCICOE PCICOE
0 1
W
Reset
16 17
R MCKOE,
MCK_
W
BOE
Reset 1 0
Table 4-35 defines the bit fields of OCCR.
Bits Name
0 PCICOE0 PCI_CLK_OUT0 enable.
0 PCI_CLK_OUT0 signal is disabled (drive constant zero).
1 PCI_CLK_OUT0 signal is enabled to toggle.
1 PCICOE1 PCI_CLK_OUT1 enable.
0 PCI_CLK_OUT1 signal is disabled (drive constant zero).
1 PCI_CLK_OUT1 signal is enabled to toggle.
2 PCICOE2 PCI_CLK_OUT2 enable.
0 PCI_CLK_OUT2 signal is disabled (drive constant zero).
1 PCI_CLK_OUT2 signal is enabled to toggle.
3–15 — Reserved, should be cleared
16 MCKOE, Enable/Disable MCK pin clock out
MCK_BOE 0 Disable MCK and MCK
1 Enable MCK and MCK
17–23 — Reserved
24 LCLK0OE Enable/Disable LCLK[0] pin clock out
0 Disable LCLK[0]
1 Enable LCLK[0]
25 LCLK1OE Enable/Disable LCLK[1] pin clock out
0 Disable LCLK[1]
1 Enable LCLK[1]
26–31 — Reserved
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
4-38
4-14, controls the device output clocks. It is possible to control some output
2 3
2
—
0 0 0 0
Figure 4-14. Output Clock Control Register (OCCR)
Table 4-35. OCCR Bit Settings
—
All zeros
23 24 25
LCLK LCLK
0OE 1OE
0 0 1 1
Description
Access: Read/Write
26
—
0 0 0 0 0
Freescale Semiconductor
15
31
0