Controlling Phy Links - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers
In the event the preamble transmission happens to cause a collision, the eTSEC ensures the minimum
96-bit presence on the wire, then drops preamble and waits a back-off time depending on the value of the
back-pressure-no-back-off configuration bit HAFDUP[BP No BackOff]. These
transmitting-preamble-for-back pressure collisions are not counted. If HAFDUP[BP No BackOff] is set,
the eTSEC waits an inter-packet gap before resuming the transmission of preamble following the collision
and does not defer. If HAFDUP[BP No BackOff] is cleared, the eTSEC adheres to the truncated BEB
algorithm that allows the possibility of packets being received. This also can be detrimental in that packets
can now experience excessive collisions, causing them to be dropped in the stations from which they
originate. To reduce the likelihood of lost packets and packets leaking through the back pressure
mechanism, HAFDUP[BP No BackOff] must be set.
The eTSEC drops carrier (cease transmitting preamble) periodically to avoid excessive defer conditions in
other stations on the shared network. If, while applying back pressure, the eTSEC is requested to send a
packet, it stops sending preamble, and waits one IPG before sending the packet. HAFDUP[BP No
BackOff] applies for any collision that occurs during the sending of this packet. Collisions for packets
while half duplex back pressure is asserted are counted. The eTSEC does not defer while attempting to
send packets while in back pressure. Again, back pressure is non-standard, yet it can be effective in
reducing the flow of receive packets.
15.5.3.4.5

Controlling PHY Links

Control and status to and from the PHY is provided through the two-wire MII management interface
described in IEEE 802.3u. The MII management registers (MII management configuration, command,
address, control, status, and indicator registers) are used to exercise this interface between a host processor
and one or more PHY devices.
The eTSEC MII's registers provide the ability to perform continuous read cycles (called a scan cycle);
although, scan cycles are not explicitly defined in the standard. If requested (by setting
MIIMCOM[Scan Cycle]), the part performs repetitive read cycles of the PHY status register, for example.
In this way, link characteristics may be monitored more efficiently. The different fields in the MII
management indicator register (scan, not valid and busy) are used to indicate availability of each read of
the scan cycle to the host from MIIMSTAT[PHY scan].
Yet another parameter that can be modified through the MII registers is the length of the MII management
interface preamble. After establishing that a PHY supports preamble suppression, the host may so
configure the eTSEC. While enabled, the length of MII management frames are reduced from 64 clocks
to 32 clocks. This effectively doubles the efficiency of the interface.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-66 Freescale Semiconductor