Endpoint Setup Status Register (Endptsetupstat)—Non-Ehci - Freescale Semiconductor MPC8313E Family Reference Manual

Table 16-25. USBMODE Register Field Descriptions (continued)
Bits Name
2 — Reserved, should be cleared.
1–0 CM Controller mode
This register can only be written once after reset. If it is necessary to switch modes, software must reset the
controller by writing to USBCMD[RST] before reprogramming this register.
00 Idle (default).
01 Reserved, should be cleared.
10 Device controller.
11 Host controller.
Defaults to the idle state and needs to be initialized to the desired operating mode after reset.
16.3.2.17 Endpoint Setup Status Register (ENDPTSETUPSTAT)—Non-EHCI
The endpoint setup status register, shown in
register contains the endpoint setup status. It is only used in device mode.
Offset 0x1AC
31
R
W
Reset
Table 16-26 describes the endpoint setup status register fields.
Bits Name
31–3 —
2–0 ENDPTSETUP
STAT
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Figure
Figure 16-23. Endpoint Setup Status (ENDPTSETUPSTAT)
Table 16-26. ENDPTSETUPSTAT Register Field Descriptions
Reserved, should be cleared.
Setup endpoint status. For every setup transaction that is received, a corresponding bit in this
register is set. Software must clear or acknowledge the setup transfer by writing a one to a respective
bit after it has read the setup data from queue head. The response to a setup packet as in the order
of operations and total response time is crucial to limit bus time outs while the setup lockout
mechanism is engaged.
This register is only used in device mode.
Description
16-23, is not defined in the EHCI specification. This
—
All zeros
Description
Universal Serial Bus Interface
Access: w1c
3 2 0
ENDPTSETUP
STAT
w1c
16-35