Freescale Semiconductor MPC8313E Family Reference Manual page 429

Request from
Address
Master
Decode
Address from
Master
CSB
DQ
Data from
SDRAM
Data from
Master
Read and write accesses to memory are burst oriented; accesses start at a selected location and continue
for a programmed number of higher locations (4 or 8) in a programmed sequence. Accesses to closed pages
start with the registration of an ACTIVE command followed by a READ or WRITE. (Accessing open
pages does not require an ACTIVE command.) The address bits registered coincident with the activate
command specifies the logical bank and row to be accessed. The address coincident with the READ or
WRITE command specify the logical bank and starting column for the burst access.
The data interface is source synchronous, meaning whatever sources the data also provides a clocking
signal to synchronize data reception. These bidirectional data strobes (MDQS[0:3] ) are inputs to the
controller during reads and outputs during writes. The DDR SDRAM specification requires the data strobe
signals to be centered within the data tenure during writes and to be offset by the controller to the center
of the data tenure during reads. This delay is implemented in the controller for both reads and writes.
The address and command interface is also source synchronous, although 1/4 cycle adjustments are
provided for adjusting the clock alignment.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Row
Open
Table
Delay Chain
Figure 9-19. DDR Memory Controller Block Diagram
Address
Control
SDRAM
Control
POS
FIFO
NEG
FIFO
DQ
SDRAM
Control
DDR Memory Controller
DDR SDRAM
Memory Array
MA[14:0]
MBA[0:2]
Debug Signals
MSRCID[0:4]
MDVAL
DDR SDRAM
Memory Control
MCS[0:1]
MCAS
MRAS
MWE
MDM[0:3]
EN
MCKE
MODT[0:1]
Data Strobes
MDQS[0:3]
Data Signals
MDQ[0:31]
EN
Clocks
MCK
MCK
9-31