Freescale Semiconductor MPC8313E Family Reference Manual page 684

Security Engine (SEC) 2.2
Bits Name
61 PD This bit must be programmed opposite to the CONT bit.
62–63 ALG Message digest algorithm selection
00 SHA-160 algorithm (full name for SHA-1)
01 SHA-256 algorithm
10 MD5 algorithm
11 SHA-224 algorithm
0
Field
Reset
R/W
Addr
Figure 14-16. MDEU Mode Register (MDEUMR) in 'New' Configuration
Table 14-18 describes MDEUMR fields in 'new' configuration.
Bits Name
The following bits are described for information only. They are not under direct user control.
0–52 — Reserved
53 STIB SSL/TLS inbound, block cipher
0 Normal operation.
1 Special operation only for SSL/TLS inbound, block cipher. Upon receiving end-of-message, the MDEU
performs a calculation involving the last valid byte of data written into its input FIFO (which is Pad Length)
to compute a final data size. The MDEU then processes the amount of data specified by this data size,
and completes the message digest.
54 NEW=1 Determines the configuration of the MDEU mode register (MDEUMR). This table shows the configuration
for NEW = 1.
55 — Reserved, must be set to zero
The following bits are controlled through the MODE0 or MODE1 fields of the descriptor header.
56 CONT Continue. Most operations will require this bit to be cleared. Set only when the data to be hashed is spread
across multiple descriptors.
0 Do autopadding and complete the message digest. Used when the entire hash is performed with one
descriptor, or on the last of a sequence of descriptors.
1 This hash will be continued in a subsequent descriptor. Do not autopad and do not complete the
message digest.
57 CICV Compare integrity check values
0 Normal operation; no ICV comparison.
1 After the message digest (ICV) is computed, compare it to the data in the MDEU's input FIFO. If the ICVs
do not match, send an error interrupt to the channel. The number of bytes to be compared is given by
the ICV size register.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
14-30
Table 14-17. MDEUMR in 'Old' Configuration (continued)
52 53
— STIB NEW=1
Table 14-18. MDEUMR in 'New' Configuration
Description
54 55 56 57
— CONT CICV SMAC INIT HMAC EALG
0
R/W
MDEU 0x3_6000
Description
58 59 60 61
Freescale Semiconductor
62 63
ALG