Freescale Semiconductor MPC8313E Family Reference Manual page 434

DDR Memory Controller
and MA[0] as the lsb. Also, MA[10] is used as the auto-precharge bit in DDR1/DDR2 modes for reads and
writes, so the column address can never use MA[10].
Table 9-27. DDR1 Address Multiplexing for 32-Bit Data Bus with Interleaving Disabled
Row
msb
x
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30–31
Col
15 x
MRAS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11 x 2
MBA
MCAS
15 x
MRAS
10 x 2
MBA
MCAS
14 x
MRAS
11 x 2
MBA
MCAS
14 x
MRAS
10 x 2
MBA
MCAS
13 x
MRAS
11 x 2
MBA
MCAS
13 x
MRAS
10 x 2
MBA
MCAS
13 x
MRAS
9 x 2
MBA
MCAS
12 x
MRAS
10 x 2
MBA
MCAS
12 x
MRAS
9 x 2
MBA
MCAS
12 x
MRAS
8 x 2
MBA
MCAS
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
9-36
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
13 12 11 10 9 8 7 6
13 12 11 10 9 8 7
12 11 10 9 8 7 6
12 11 10 9 8 7
12 11 10 9 8
11 10 9 8 7
11 10 9 8
11 10 9
Address from Core Master
1 0
1 0
5 4 3 2 1 0
1 0
6 5 4 3 2 1 0
1
5 4 3 2 1 0
1 0
6 5 4 3 2 1 0
1
7 6 5 4 3 2 1 0
6 5 4 3 2 1 0
1
7 6 5 4 3 2 1 0
8 7 6 5 4 3 2 1
11 9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
11 9 8 7 6 5 4 3
0
9 8 7 6 5 4 3
11 9 8 7 6 5 4 3
0
9 8 7 6 5 4 3
1 0
8 7 6 5 4 3
0
9 8 7 6 5 4 3
1 0
8 7 6 5 4 3
0
1 0
7 6 5 4 3
Freescale Semiconductor
lsb
2 1 0
2 1 0
2 1 0
2 1 0
2 1 0
2 1 0
2 1 0
2 1 0