Transmit Multiple Collision Packet Counter (Tmcl); Transmit Late Collision Packet Counter (Tlcl) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers

15.5.3.6.33 Transmit Multiple Collision Packet Counter (TMCL)

Figure 15-85 describes the definition for the TMCL register.
Offset eTSEC1:0x2_4700; eTSEC2:0x2_5700
0
R
W
Reset
Figure 15-85. Transmit Multiple Collision Packet Counter Register Definition
Table 15-89 describes the fields of the TMCL register.
Bits Name
0–19 — Reserved
20–31 TMCL Transmit multiple collision packet counter. Increments for each frame transmitted which experienced 2–15
collisions (including any late collisions) during transmission as defined using the
Half_Duplex[RETRANSMISSION MAXIMUM] field.

15.5.3.6.34 Transmit Late Collision Packet Counter (TLCL)

Figure 15-86 describes the definition for the TLCL register.
Offset eTSEC1:0x2_4704; eTSEC2:0x2_5704
0
R
W
Reset
Figure 15-86. Transmit Late Collision Packet Counter Register Definition
Table 15-90 describes the fields of the TLCL register.
Bits Name
0–19 — Reserved
20–31 TLCL Transmit late collision packet counter. Increments for each frame transmitted which experienced a late
collision during a transmission attempt. Late collisions are defined using the collision window field of the
half-duplex [26:31] register.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-96
—
All zeros
Table 15-89. TMCL Field Descriptions
Description
—
All zeros
Table 15-90. TLCL Field Descriptions
Description
Access: Read/Write
19 20
TMCL
Access: Read/Write
19 20
TLCL
Freescale Semiconductor
31
31