Freescale Semiconductor MPC8313E Family Reference Manual page 471

Bits Name
24 CHT Command hold time. Determines the LFWE negation prior to the command, address, or data change when
the external memory access is handled by the FCM.
TRLX
25–27 SCY Cycle length in bus clocks. Determines the following:
• the number of wait states inserted in command, address, or data transfer bus cycles, when the FCM
handles the external memory access. Thus it is the main parameter for determining cycle length. The
total cycle length depends on other timing attribute settings.
• the delay between command/address writes and data write cycles, or the delay between write cycles and
read cycles from NAND Flash EEPROM. A delay of 4×(2+SCY) clock cycles (TRLX = 0) or 8×(2+SCY)
clock cycles (TRLX = 1) is inserted between the last write and the first data transfer to/from NAND Flash
devices.
• the delay between a command write and the first sample point of the RDY/BSY pin (connected to LFRB).
LFRB is not sampled until 8×(2+SCY) clock cycles (TRLX = 0) or 16×(2+SCY) clock cycles (TRLX = 1)
have elapsed following the command.
000 No extra wait states
001 1 bus clock cycle wait state
...
111 7 bus clock cycle wait states
28 RST Read setup time. Determines the delay of LFRE assertion relative to sampling of read data when the
external memory access is handled by the FCM.
TRLX
29 TRLX Timing relaxed. Modifies the settings of timing parameters for slow memories.
0 Normal timing is generated by the FCM.
1 Relaxed timing on the following parameters:
• Doubles the number of clock cycles between LCS n assertion and commands.
• Doubles the number of wait states specified by SCY, providing up to 14 wait states.
• Works in conjunction with CST and RST to extend command/address/data setup times.
• Adds one clock cycle to the command/address/data hold times.
• Works in conjunction with CBT to extend the wait time for read/busy status sampling by 16 clock cycles.
• Works in conjunction with EHTR to double hold time on read accesses.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
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Table 10-8. OR n FCM Field Descriptions (continued)
CHT
0 0 The write-enable is negated 0.5 clock cycles before any command, address, or
data change.
0 1 The write-enable is negated 1 clock cycle before any command, address, or data
change.
1 0 The write-enable is negated 1.5 clock cycles before any command, address, or
data change.
1 1 The write-enable is negated 2 clock cycles before any command, address, or
data change.
RST
0 0 The read-enable is asserted 0.75 clock cycles prior to any wait states.
0 1 The read-enable is asserted 1 clock cycle prior to any wait states.
1 0 The read-enable is asserted 0.5 clock cycles prior to any wait states.
1 1 The read-enable is asserted 1 clock cycle prior to any wait states.
Description
Meaning
Meaning
Enhanced Local Bus Controller
10-17