Freescale Semiconductor MPC8313E Family Reference Manual page 46

Figure
Number
13-4 PCI_CONFIG_DATA ......................................................................................................... 13-15
13-5 PCI Error Status Register (PCI_ESR)................................................................................. 13-15
13-6 PCI Error Capture Disable Register (PCI_ECDR) ............................................................. 13-16
13-7 PCI Error Enable Register (PCI_EER) ............................................................................... 13-17
13-8 PCI Error Attributes Capture Register (PCI_EATCR) ....................................................... 13-18
13-9 PCI Error Address Capture Register (PCI_EACR) ............................................................ 13-19
13-10 PCI Error Extended Address Capture Register (PCI_EEACR).......................................... 13-20
13-11 PCI Error Data Low Capture Register (PCI_EDLCR) ....................................................... 13-20
13-12 PCI General Control Register (PCI_GCR) ......................................................................... 13-21
13-13 PCI Error Control Register (PCI_ECR).............................................................................. 13-21
13-14 PCI General Status Register (PCI_GSR) ............................................................................ 13-22
13-15 PCI Inbound Translation Address Registers (PITARn) ...................................................... 13-23
13-16 PCI Inbound Base Address Registers (PIBARn) ................................................................ 13-23
13-17 PCI Inbound Extended Base Address Registers (PIEBARn) ............................................. 13-24
13-18 PCI Inbound Window Attribute Registers (PIWARn) ........................................................ 13-24
13-19 Vendor ID Configuration Register ...................................................................................... 13-27
13-20 Device ID Configuration Register ...................................................................................... 13-27
13-21 PCI Command Configuration Register ............................................................................... 13-28
13-22 PCI Status Configuration Register ...................................................................................... 13-29
13-23 Revision ID Configuration Register ................................................................................... 13-30
13-24 Standard Programming Interface Configuration Register................................................... 13-30
13-25 Subclass Code Configuration Register ............................................................................... 13-31
13-26 Base Class Code Configuration Register ............................................................................ 13-31
13-27 Cache Line Size Configuration Register............................................................................. 13-32
13-28 Latency Timer Configuration Register ............................................................................... 13-32
13-29 Header Type Configuration Register .................................................................................. 13-33
13-30 BIST Control Configuration Register ................................................................................. 13-33
13-31 PIMMR Base Address Configuration Register................................................................... 13-33
13-32 GPL Base Address Register 0 ............................................................................................. 13-34
13-33 GPL Base Address Registers 1–2 ....................................................................................... 13-35
13-34 GPL Extended Base Address Registers 1–2 ....................................................................... 13-35
13-35 Subsystem Vendor ID Configuration Register.................................................................... 13-36
13-36 Subsystem Device ID Configuration Register .................................................................... 13-36
13-37 Capabilities Pointer Configuration Register ....................................................................... 13-37
13-38 Interrupt Line Configuration Register................................................................................. 13-37
13-39 Interrupt Pin Register .......................................................................................................... 13-37
13-40 Minimum Grant Configuration Register............................................................................. 13-38
13-41 Maximum Latency Configuration Register ........................................................................ 13-38
13-42 PCI Function Configuration Register ................................................................................. 13-38
13-43 PCI Arbiter Control Register (PCIACR) ............................................................................ 13-39
13-44 Hot Swap Register Block .................................................................................................... 13-40
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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