Host Controller Initialization - Freescale Semiconductor MPC8313E Family Reference Manual

between system software and host controller hardware. Information concerning the initialization of the
USB module is included in the following section; however, the full details of the EHCI specification are
beyond the scope of this document.
16.6.1

Host Controller Initialization

After initial power-on or host controller reset (hardware or through USBCMD[RST]), all of the operational
registers are at their default values.
The MPC8313E USB PHY and clock must be configured prior to initialization of the USB controller.
Initialization of the MPC8313E USB PHY interface is performed through software control following a
power-on reset.
The device can be configured for either the internal UTMI PHY or an external ULPI PHY enabled with
various clocking options. The configuration of each PHY interface and the various clocking options are
detailed below:
To configure the internal UTMI PHY, the following initialization sequence is required:
1. After power-on reset, the UTMI PHY will be in disabled state and the PLL will be held reset.
2. Set the CONTROL[REFSEL] bits to correspond to the appropriate UTMI PLL reference clock
frequency.
3. Set the CONTROL[CLKIN_SEL] bits to select the source and divider of the UTMI reference
clock.
4. Set the CONTROL[PHY_CLK_SEL] bits to select the UTMI PHY as the source of USB controller
PHY clock.
5. Set the CONTROL[UTMI_PHY_EN] to enable the UTMI PHY and release the PLL.
6. Wait for PHY clock to become valid. This can be determined by polling the
CONTROL[PHY_CLK_VALID] status bit.
Once the PHY clock is valid the user can proceed to the host controller initialization phase.
To configure the external ULPI PHY the following initialization sequence is required:
1. The UTMI PHY should remain disabled if the ULPI is being used.
2. Set the CONTROL[PHY_CLK_SEL] bits to select the ULPI PHY as the source of USB controller
PHY clock.
3. Wait for PHY clock to become valid. This can be determined by polling the
CONTROL[PHY_CLK_VALID] status bit. Note that this bit is not valid once the
CONTROL[USB_EN] bit is set
Once the PHY clock is valid the user can proceed to the host controller initialization phase.
In order to initialize the USB DR module, software should perform the following steps:
1. Set the controller mode to host mode. Optionally set USBMODE[SDIS] (streaming disable)
Transitioning from device mode to host mode requires a host controller reset
before modifying USBMODE.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
NOTE
Universal Serial Bus Interface
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