Freescale Semiconductor MPC8313E Family Reference Manual page 782

Enhanced Three-Speed Ethernet Controllers
Bits Name
9 QHLT1 RxBD queue 1 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
not cause a QHLT1 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
10 QHLT2 RxBD queue 2 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
not cause a QHLT2 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
11 QHLT3 RxBD queue 3 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
not cause a QHLT3 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
12 QHLT4 RxBD queue 4 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
not cause a QHLT4 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
13 QHLT5 RxBD queue 5 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
not cause a QHLT5 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
14 QHLT6 RxBD queue 6 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
not cause a QHLT6 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
15 QHLT7 RxBD queue 7 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
not cause a QHLT7 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
16–23 — Reserved
24 RXF0 Receive frame event occurred on ring 0. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
25 RXF1 Receive frame event occurred on ring 1. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
26 RXF2 Receive frame event occurred on ring 2. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
27 RXF3 Receive frame event occurred on ring 3. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
28 RXF4 Receive frame event occurred on ring 4. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-52
Table 15-29. RSTAT Field Descriptions (continued)
Description
Freescale Semiconductor