Freescale Semiconductor MPC8313E Family Reference Manual page 4

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Number
2.1 Internal Memory Mapped Registers ................................................................................ 2-1
2.2 Accessing IMMR Memory From the Local Processor .................................................... 2-1
2.3 Complete IMMR Map ..................................................................................................... 2-1
3.1 Signals Overview ............................................................................................................. 3-1
3.2 Configuration Signals Sampled at Reset ....................................................................... 3-29
3.3 Output Signal States During Reset ................................................................................ 3-30
3.4 External Signal Description ........................................................................................... 3-32
4.1 External Signals ............................................................................................................... 4-1
4.1.1 Reset Signals................................................................................................................ 4-1
4.1.2 Clock Signals ............................................................................................................... 4-3
4.2 Functional Description..................................................................................................... 4-4
4.2.1 Reset Operations .......................................................................................................... 4-4
4.2.1.1 Reset Causes ............................................................................................................ 4-5
4.2.1.2 Reset Actions ........................................................................................................... 4-5
4.2.2 Power-On Reset Flow.................................................................................................. 4-6
4.2.3 Hard Reset Flow .......................................................................................................... 4-8
4.2.4 Soft Reset Flow............................................................................................................ 4-9
4.3 Reset Configuration ......................................................................................................... 4-9
4.3.1 Reset Configuration Signals ........................................................................................ 4-9
4.3.1.1 Reset Configuration Word Source ......................................................................... 4-10
4.3.1.2 SYS_CLK_IN Division ......................................................................................... 4-11
4.3.1.3 Selecting Reset Configuration Input Signals ......................................................... 4-11
4.3.2 Reset Configuration Words........................................................................................ 4-12
4.3.2.1 Reset Configuration Word Low Register (RCWLR)............................................. 4-13
4.3.2.1.1
4.3.2.2 Reset Configuration Word High Register (RCWHR)............................................ 4-15
4.3.2.2.1
4.3.2.2.2
4.3.2.2.3
4.3.2.2.4
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
iv
Contents
Signal Descriptions
Reset, Clocking, and Initialization
System PLL Configuration................................................................................ 4-14
PCI Host/Agent Configuration .......................................................................... 4-16
Boot Memory Space (BMS) .............................................................................. 4-17
Boot Sequencer Configuration .......................................................................... 4-17
Boot ROM Location .......................................................................................... 4-18
Title
Chapter 2
Memory Map
Chapter 3
Chapter 4
Page
Number
Freescale Semiconductor