Pci Error Enable Register (Pci_Eer) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor
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Table 13-9
describes the bit settings of the PCI_ECDR register.
Bits
Name
0–20
21
APAR
22
PCISERR PCI system error. Disable capture for received PCI_SERR errors
23
MPERR
24
TPERR
25
NORSP
26
TABT
27–31
13.3.2.3

PCI Error Enable Register (PCI_EER)

PCI_EER contains fields for enabling the assertion of an interrupt for the error conditions reported in the
PCI error status register (PCI_ESR).
1 = The interrupt is enabled.
0 = The interrupt is disabled.
Figure 13-7
shows the PCI_EER fields.
Offset 0x08
0
R
W
Reset
Table 13-10
describes the bit settings of the PCI_EER register.
Bits
Name
0–20
21
APAR
22
PCISERR PCI system error. Generate an interrupt when the corresponding bit of the PCI_ESR is 1.
23
MPERR
24
TPERR
25
NORSP
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 13-9. PCI_ECDR Field Descriptions
Reserved
Address parity error. Disable capture for address parity errors
Master parity error. Disable capture for master PCI_PERR errors
Target parity error. Disable capture for target PCI_PERR errors
No response. Disable capture for master-abort errors
Target abort. Disable capture for target abort errors
Reserved
Figure 13-7. PCI Error Enable Register (PCI_EER)
Table 13-10. PCI_EER Field Descriptions
Reserved
Address parity error. Generate an interrupt when the corresponding bit of the PCI_ESR is 1.
Master parity error. Generate an interrupt when the corresponding bit of the PCI_ESR is 1.
Target parity error. Generate an interrupt when the corresponding bit of the PCI_ESR is 1.
No response. Generate an interrupt when the corresponding bit of the PCI_ESR is 1.
Description
20
21
22
23
APAR PCISERR MPERR TPERR NORSP TABT
All zeros
Description
PCI Bus Interface
Access: Read/Write
24
25
26
27
31
13-17

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