Freescale Semiconductor MPC8313E Family Reference Manual page 560

Enhanced Local Bus Controller
mostly used by performance-critical applications, it is assumed here that, typically, the maximum width of
the local bus of 16 bits will be used.
ZBT SRAMs allow different configurations. For the local bus, the burst order should be set to linear burst
order by tying the mode pin to GND. CKE should also be tied to ground.
ZBT SRAMs perform four-beat bursts. Because the eLBC generates sixteen-beat transactions (for 16-bit
ports) the UPM breaks down each burst into four consecutive four-beat bursts. The internal address
generator of the eLBC generates the new {A21, A22} for the second, third, and fourth burst. In other
words, because linear burst is used on the SRAM, the device itself bursts with the burst addresses of
[0:1:2:3]. The local bus always generates linear bursts and expects [0:1:2:3:4:5:6:7:...:15]. Therefore, four
consecutive linear bursts of the ZBT SRAM with {A21, A22} = {0,0} for the first burst, {A21,
A22} = {0,1} for the second burst, {A21, A22} = {1,0} for the third burst, and {A21, A22} = {1,1} for
the fourth burst give the desired burst pattern.
The UPM also supports single beat accesses. Because the ZBT SRAM does not support this and always
responds with a burst, the UPM pattern has to take care that data for the critical beat is provided (for write)
or sampled (for read), and that the rest of the burst is ignored (by negating WE). The UPM controller
basically has to wait for the end of the SRAM burst to avoid bus contention with further bus activities.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
10-106
Local Bus Interface
LBS[0:1]
LCS n
LGPL0
LGPL1
LGPL2
GPIO
LA n
LALE
LAD[0:15]
LCLK
Figure 10-80. Interface to ZBT SRAM
BW[0:1]
Latch
DATA[0:15]
1M × 18
ZBT
SRAM
OE
CE
ADV/LD
WE
ZZ
BW[0:1]
MODE
CKE
CLK
SA[19:0]
DQ[0:17]
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