System External Interrupt Control Register (Secnr) - Freescale Semiconductor MPC8313E Family Reference Manual

Table 8-19 defines the bit fields of SEMSR.
Bits Name
IRQ n
0–4 Each bit corresponds to an external interrupt source. The user masks an interrupt by clearing the SEMSR bit.
An interrupt can be enabled by setting the corresponding SEMSR bit.
SEMSR can be read by the user at any time.
Note:
• SEMSR bit positions are not affected by their relative priority.
• The user can clear pending register bits that were set by multiple interrupt events only by clearing all
unmasked events in the corresponding event register.
• If an SEMSR bit is masked at the same time that the corresponding SEPNR bit causes an interrupt request
to the core, the error vector is issued (if no other interrupts pending). Thus, the user must always include an
error vector routine, even if it contains only an rfi instruction. The error vector cannot be masked.
5–15 — Write ignored, read = 0
16 SIRQ0 Steer IRQ0.
0 IRQ0 is used as external interrupt request
1 IRQ0 is used as external MCP request
17–31 — Write ignored, read = 0
8.5.12

System External Interrupt Control Register (SECNR)

SECNR, shown in Figure
determines whether the corresponding IRQn signal asserts an interrupt request upon either a high-to-low
change or assertion on the pin. It also defines the IPIC output interrupt type (int, cint, or smi) in the
MIXA0–MIXA1 and MIXB0–MIXB1 priority positions.
Note that in core disabled mode of operation the user should use the int output interrupt type (should not
use cint or smi output interrupt types) in order to read an updated SIVCR.
Offset 0x3C
0 1 2
R
MIXB0T MIXB1T
W
Reset
16 17 18
R
EDI0 EDI1 EDI2
W
Reset
Figure 8-15. System External Interrupt Control Register (SECNR)
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 8-19. SEMSR Field Descriptions
8-15, defines the edge detect mode for external IRQn interrupt signals and
3 4
—
19 20 21 22
EDI3 EDI4 EDI5 EDI6
Integrated Programmable Interrupt Controller (IPIC)
Description
7 8 9 10
MIXA0T MIXA1T
All zeros
23 24
EDI7
All zeros
Access: Read/write
11 12
—
—
15
31
8-21