Freescale Semiconductor MPC8313E Family Reference Manual page 263

Name Port
TIN1 TIN1
TIN2 TIN2
TIN3 TIN3
TIN4 TIN4
TGATE1 TGATE1
TGATE2 TGATE2
TGATE3 TGATE3
TGATE4 TGATE4
TOUT1 TOUT1
TOUT2 TOUT2
TOUT3 TOUT3
TOUT4 TOUT4
Table 5-54 provides detailed descriptions of the external GTM signals.
Table 5-54. GTM External Signals—Detailed Signal Descriptions
Signal I/O
TIN n
I Global timer capture control signal. Used to latch the value of the counter when a defined transition of
TIN n is sensed by the corresponding input capture edge detector.
Meaning
Timing Assertion/Negation—Asynchronous to internal bus clock. TIN n is internally synchronized to
TGATE n
I Global timer counter gate control signal. Used to gate/restart the counter when a defined transition of
TGATE n is sensed by the corresponding input capture edge detector.
Meaning
Timing Assertion/Negation—Asynchronous to internal bus clock. TGATE n is internally
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 5-53. GTM Signal Properties
Global timer 1 capture control signal
Global timer 2 capture control signal
Global timer 3 capture control signal
Global timer 4 capture control signal
Global timer 1 counter gate control signal
Global timer 2 counter gate control signal
Global timer 3 counter gate control signal
Global timer 4 counter gate control signal
Global timer 1 counter output signal
Global timer 2 counter output signal
Global timer 3 counter output signal
Global timer 4 counter output signal
State Asserted/Negated —According to the programmed polarity by the corresponding
GTMDR n [CE]). Each timer has a 16-bit GTCPR used to latch the value of the counter
when a defined transition of TIN n is sensed by the corresponding input capture edge
detector. Upon a capture or reference event, the corresponding GTEVR bit is set and
a maskable interrupt request is issued to the interrupt controller.
the system bus clock. If TIN n meets the asynchronous input setup time, the value of
counter is captured after one system bus clock when working with the internal clock.
State Asserted/Negated—According to the programmed polarity by the corresponding
GTCFR[GMx] bits. In a restart gate mode (GTCFR[GM n ] = 0), the TGATE n pin is used
to enable/disable count. A falling TGATE n pin enables and restarts the count and a
rising edge of TGATE n disables the count. In a normal gate mode (GTCFR[GM n ] = 1),
the TGATE n have similar functionality, except the falling edge of TGATE n does not
restart the appropriate count value in GTCNR n [CNV n ].
synchronized to the system bus clock. If TGATE n meets the asynchronous input setup
time, the counter begins counting or stops counting (depending on the signal state and
the configured mode) after one system bus clock when working with the internal clock.
Function
Description
System Configuration
Require
I/O Reset
Pull Up
I 0 No
I 0 No
I 0 No
I 0 No
I 0 No
I 0 No
I 0 No
I 0 No
O 1 No
O 1 No
O 1 No
O 1 No
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