Freescale Semiconductor MPC8313E Family Reference Manual page 739

Table 15-2. eTSEC Signals—Detailed Signal Descriptions (continued)
Signal I/O
EC_GTX_CLK125
EC_MDC O
EC_MDIO I/O Management data input/output.
TSEC n _RX_CLK
TSEC n _RX_DV
TSEC n _RXD[3:0]
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
I Gigabit transmit 125-MHz source. This signal must be generated externally with a crystal or
oscillator, or is sometimes provided by the PHY. EC_GTX_CLK125 is a 125-MHz input into the
eTSEC and is used to generate all 125-MHz related signals and clocks in the following modes:
• RTBI
• RGMII
This input is not used in these modes:
• RMII
• SGMII
• MII
Management data clock.
This signal is a clock (typically 2.5 MHz) supplied by the MAC
(IEEE set minimum period of 400 ns or a frequency of 2.5 MHz, but the device may be configured
up to 12.5 MHz if supported by the PHY at that speed.) The frequency can be modified by writing
to MIIMCFG[28:31] of the eTSEC1 controller.
State Asserted/Negated—EC_MDIO is a bidirectional signal to input PHY-supplied status
Meaning during management read cycles and output control during MII management write
cycles. Addressed using eTSEC1 memory-mapped registers.
Timing Asserted/Negated—This signal is required to be synchronous with the EC_MDC
signal.
I Receive clock. In MII or RGMII mode, the receive clock TSEC n _RX_CLK is a continuous clock
(2.5, 25, or 125 MHz) that provides a timing reference for TSEC n _RX_DV, TSEC n _RXD, and
TSEC n _RX_ER.
In RTBI mode it is a 125-MHz receive clock.
In RMII mode this clock is not used for the receive clock, as RMII uses a shared reference clock.
I Receive data valid. In MII mode, if TSEC n _RX_DV is asserted, the PHY is indicating that valid
data is present on the MII interface.
In RGMII mode, TSEC n _RX_DV becomes RX_CTL. The RX_DV and RX_ERR are received on
this signal on the rising and falling edges of TSEC n _RX_CLK.
In RTBI mode, TSEC n _RX_DV represents receive code group (RCG) bit 4 and 9. On the positive
edge of the TSEC n _RX_CLK, RCG[4] and RCG[3:0] represent the first half of the 10-bit encoded
symbol. On the negative edge of the TSEC n _RX_CLK, RCG[9] and RCG[8:5] represent the
second half of the 10-bit encoded symbol.
In RMII mode the PHY asserts TSEC n _RX_DV (CRS_DV) when the receive medium is non-idle.
This signal asserts asynchronously with respect to the RMII reference clock, but negates
synchronously to indicate loss of carrier.
I Receive data in. In MII mode, TSEC n _RXD[3:0] represents a nibble of data to be transferred from
the PHY to the MAC when TSEC n _RX_DV is asserted. A completely-formed SFD must be
passed across the MII. While TSEC n _RX_DV is not asserted, TSEC n _RXD has no meaning.
In RGMII mode, data bits 3:0 are received on the rising edge of TSEC n _RX_CLK and data bits
7:4 are received on the falling edge of TSEC n _RX_CLK.
In RTBI mode, TSEC n _RXD[3:0] represents RCG[3:0] on the rising edge of TSEC n _RX_CLK
and RCG[8:5] are received on the falling edge of TSEC n _RX_CLK.
In RMII mode, TSEC n _RXD[1:0] represents RXD[1:0], which is considered valid when
TSEC n _RX_DV (CRS_DV) is asserted, or invalid otherwise.
Enhanced Three-Speed Ethernet Controllers
Description
15-9