Freescale Semiconductor MPC8313E Family Reference Manual page 36

Paragraph
Number
18.4.1.1 START Bit ........................................................................................................... 18-19
18.4.1.2 Data Transfer ....................................................................................................... 18-19
18.4.1.3 Parity Bit .............................................................................................................. 18-19
18.4.1.4 STOP Bit.............................................................................................................. 18-20
18.4.2 Baud-Rate Generator Logic ..................................................................................... 18-20
18.4.3 Local Loopback Mode ............................................................................................. 18-20
18.4.4 Errors ....................................................................................................................... 18-21
18.4.4.1 Framing Error ...................................................................................................... 18-21
18.4.4.2 Parity Error .......................................................................................................... 18-21
18.4.4.3 Overrun Error....................................................................................................... 18-21
18.4.5 FIFO Mode .............................................................................................................. 18-21
18.4.5.1 FIFO Interrupts .................................................................................................... 18-21
18.4.5.2 DMA Mode Select ............................................................................................... 18-22
18.4.5.3 Interrupt Control Logic........................................................................................ 18-22
18.5 DUART Initialization/Application Information .......................................................... 18-22
19.1 Overview........................................................................................................................ 19-1
19.2 Introduction.................................................................................................................... 19-2
19.2.1 Features...................................................................................................................... 19-2
19.2.2 SPI Transmission and Reception Process .................................................................. 19-3
19.2.3 Modes of Operation ................................................................................................... 19-3
19.2.3.1 SPI as a Master Device .......................................................................................... 19-3
19.2.3.2 SPI as a Slave Device ............................................................................................ 19-4
19.2.3.3 SPI in Multiple-Master Operation ......................................................................... 19-5
19.3 External Signal Descriptions ......................................................................................... 19-6
19.3.1 Overview.................................................................................................................... 19-7
19.3.2 Detailed Signal Descriptions ..................................................................................... 19-7
19.4 Memory Map/Register Definition ................................................................................. 19-8
19.4.1 Register Descriptions................................................................................................. 19-9
19.4.1.1 SPI Mode Register (SPMODE) ............................................................................. 19-9
19.4.1.2 SPI Event Register (SPIE) ................................................................................... 19-11
19.4.1.3 SPI Mask Register (SPIM) .................................................................................. 19-12
19.4.1.4 SPI Command Register (SPCOM) ...................................................................... 19-14
19.4.1.5 SPI Transmit Data Hold Register (SPITD).......................................................... 19-14
19.4.1.6 SPI Receive Data Hold Register (SPIRD)........................................................... 19-15
19.4.1.6.1
19.5 Initialization/Application Information ......................................................................... 19-16
19.5.1 SPI Master Programming Example ......................................................................... 19-16
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
xxxvi
Contents
Serial Peripheral Interface
Reverse Mode SPMODE[REV] Examples ..................................................... 19-15
Title
Chapter 19
Page
Number
Freescale Semiconductor